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* [PATCH, BINUTILS, AARCH64, 2/9] Add Data procoessing instructions for ARMv8.5-ASudakshina Das2018-10-095-2644/+2766
* [PATCH, BINUTILS, AARCH64, 1/9] Add -march=armv8.5-a and related internal fea...Sudakshina Das2018-10-092-0/+11
* AArch64: Replace C initializers with memsetTamar Christina2018-10-082-1/+7
* x86: Add Intel ENCLV to assembler and disassemblerH.J. Lu2018-10-054-1/+22
* [Arm, 2/3] Add instruction SB for AArch32Sudakshina Das2018-10-052-0/+11
* or1k: Add the l.muld, l.muldu, l.macu, l.msbu insnsRichard Henderson2018-10-056-29/+163
* or1k: Add the l.adrp insn and supporting relocationsStafford Horne2018-10-059-137/+320
* or1k: Add relocations for high-signed and low-storesRichard Henderson2018-10-052-272/+172
* AArch64: Constraint disassembler and assembler changes.Tamar Christina2018-10-034-11/+104
* AArch64: Add SVE constraints verifier.Tamar Christina2018-10-033-1/+358
* AArch64: Refactor verifiers to make more general.Tamar Christina2018-10-033-7/+16
* AArch64: Refactor err_type.Tamar Christina2018-10-032-13/+13
* AArch64: Wire through instr_sequenceTamar Christina2018-10-033-1/+10
* AArch64: Mark sve instructions that require MOVPRFX constraintsTamar Christina2018-10-032-231/+254
* RISC-V: Add fence.tso instructionPalmer Dabbelt2018-10-022-0/+5
* Fix incorrect extraction of signed constants in nios2 disassembler.Sandra Loosemore2018-09-232-13/+21
* csky-opc.h: Initialize fields of last array elementsSimon Marchi2018-09-217-68/+14
* ARC: Fix build errors with large constants and C89Maciej W. Rozycki2018-09-202-26/+30
* Andes Technology has good news for you, we plan to update the nds32 port of b...Nick Clifton2018-09-205-300/+944
* RISC-V: bge[u] should get higher priority than ble[u].Jim Wilson2018-09-172-2/+6
* x86: Set EVex=2 on EVEX.128 only vmovd and vmovqH.J. Lu2018-09-175-13/+94
* x86: Set Vex=1 on VEX.128 only vmovd and vmovqH.J. Lu2018-09-174-18/+24
* x86: Update disassembler for VexWIGH.J. Lu2018-09-172-1563/+619
* x86: Replace VexW=3 with VexWIGH.J. Lu2018-09-172-468/+475
* x86: Set VexW=3 on AVX vrsqrtssH.J. Lu2018-09-153-2/+7
* x86: Set Vex=1 on VEX.128 only vmovqH.J. Lu2018-09-154-6/+12
* x86: Support VEX/EVEX WIG encodingH.J. Lu2018-09-144-932/+941
* x86: Handle unsupported static rounding in vcvt[u]si2sd in 32-bit modeH.J. Lu2018-09-143-2/+22
* x86: Properly decode EVEX.W in vcvt[u]si2s[sd] in 32-bit modeH.J. Lu2018-09-143-4/+23
* i386: Reformat OP_E_memoryH.J. Lu2018-09-142-2/+6
* x86: fold CRC32 templatesJan Beulich2018-09-143-45/+12
* x86: Remove VexW=1 from WIG VEX movq and vmovqH.J. Lu2018-09-132-8/+8
* i386: Update VexW field for VEX instructionsH.J. Lu2018-09-133-36/+44
* x86: drop bogus IgnoreSize from a few further insnsJan Beulich2018-09-133-52/+61
* x86: drop bogus IgnoreSize from AVX512_4* insnsJan Beulich2018-09-133-12/+18
* x86: drop bogus IgnoreSize from AVX512DQ insnsJan Beulich2018-09-133-96/+102
* x86: drop bogus IgnoreSize from AVX512BW insnsJan Beulich2018-09-133-78/+84
* x86: drop bogus IgnoreSize from AVX512VL insnsJan Beulich2018-09-133-26/+32
* x86: drop bogus IgnoreSize from AVX512ER insnsJan Beulich2018-09-133-32/+38
* x86: drop bogus IgnoreSize from AVX512F insnsJan Beulich2018-09-133-742/+748
* x86: drop bogus IgnoreSize from SHA insnsJan Beulich2018-09-133-16/+21
* x86: drop bogus IgnoreSize from XOP and SSE4a insnsJan Beulich2018-09-133-266/+271
* x86: drop bogus IgnoreSize from AVX2 insnsJan Beulich2018-09-133-238/+244
* x86: drop bogus IgnoreSize from AVX insnsJan Beulich2018-09-133-256/+262
* x86: drop bogus IgnoreSize from GNFI insnsJan Beulich2018-09-133-12/+17
* x86: drop bogus IgnoreSize from PCLMUL/VPCLMUL insnsJan Beulich2018-09-133-32/+37
* x86: drop bogus IgnoreSize from AES/VAES insnsJan Beulich2018-09-133-44/+49
* x86: drop bogus IgnoreSize from SSE4.2 insnsJan Beulich2018-09-133-20/+26
* x86: drop bogus IgnoreSize from SSE4.1 insnsJan Beulich2018-09-133-126/+132
* x86: drop bogus IgnoreSize from SSSE3 insnsJan Beulich2018-09-133-64/+70