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* Re: nios2: Remove binutils support for Nios II targetAlan Modra2024-11-271-2/+0
* nios2: Remove binutils support for Nios II target.Sandra Loosemore2024-11-268-1846/+0
* opcodes: fix Werror=format build breaker in opcodes/riscv-dis.cTom de Vries2024-11-241-1/+1
* RISC-V: Support SiFive extensions: xsfvqmaccdod, xsfvqmaccqoq and xsfvfnrclip...Nelson Chu2024-11-221-0/+14
* PowerPC: Add support for RFC02677 - VSX Vector Rotate Left WordPeter Bergner2024-11-201-0/+1
* arm: Support pac_key_* register operand for MRS/MSR in Armv8.1-M MainlineAndre Vieira2024-11-201-4/+27
* RISC-V: Add Zcmt instructions and csr.Jiawei2024-11-202-0/+28
* Support x86 Intel MSR_IMMHu, Lin12024-11-196-833/+914
* x86: rename SPACE_{,E}VEX_MAP<N>Jan Beulich2024-11-184-744/+744
* x86: VP2INTERSECT{D,Q} have mask register destination groupJan Beulich2024-11-182-3/+3
* x86: generalize "implicit quad group" handlingJan Beulich2024-11-182-10/+12
* s390: Add arch15 Concurrent-Functions Facility insnsJens Remus2024-11-182-0/+10
* s390: Add arch15 instruction namesJens Remus2024-11-181-106/+114
* opcodes: fix -std=gnu23 compatibility wrt static_assertSam James2024-11-183-3/+7
* aarch64: add flag OPD_F_UNSIGNED to distinguish signedness of immediate operandsMatthieu Longo2024-11-082-23/+77
* aarch64: improve debuggability on array of enumMatthieu Longo2024-11-081-3/+3
* aarch64: change returned type to bool to match semantic of functionsMatthieu Longo2024-11-082-172/+172
* arm, objdump: print obsolote warning when 26-bit set in instructionsAndre Vieira2024-11-081-25/+19
* arm, objdump: Make objdump use bfd's machine detection to drive disassemblyAndre Vieira2024-11-081-4/+23
* RISC-V: Dump instruction without checking architecture support as usual.Nelson Chu2024-10-311-1/+7
* x86/APX: support JMPABS also in assemblerJan Beulich2024-10-303-903/+924
* x86: use <xyz> for VFPCLASSP{S,D}Jan Beulich2024-10-292-35/+31
* x86: Regenerate missing table filesMayShao-oc2024-10-183-4388/+4428
* x86: Support x86 ZHAOXIN GMI instructionsMayShao-oc2024-10-184-1/+56
* Support Intel AVX10.2 convert instructionsLiwei Xu2024-10-166-1996/+2488
* x86: also template-expand trailing mnemonic partJan Beulich2024-10-141-60/+72
* LoongArch: Fixed R_LARCH_[32/64]_PCREL generation bugLulu Cai2024-10-141-1/+2
* Support Intel AVX10.2 media instructionsHaochen Jiang2024-10-117-702/+893
* s390: Add arch15 instructionsAndreas Krebbel2024-10-103-3/+127
* m68k: Support for jump visualization in disassemblyAndreas Schwab2024-10-071-0/+27
* RISC-V: correct alignment directive handling for text sectionsJan Beulich2024-09-271-1/+1
* x86: optimize {,V}INSERTPS with certain immediatesJan Beulich2024-09-272-7/+7
* x86: optimize {,V}EXTRACT{F,I}{128,32x{4,8},64x{2,4}} with immediate 0Jan Beulich2024-09-272-20/+20
* x86: optimize {,V}EXTRACTPS with immediate 0Jan Beulich2024-09-272-12/+12
* x86: templatize SIMD narrowing-move templatesJan Beulich2024-09-262-72/+32
* x86: templatize SIMD sign-/zero-extension templatesJan Beulich2024-09-262-251/+220
* x86: templatize SIMD FP binary-logic templatesJan Beulich2024-09-262-282/+271
* x86: further templatize FMA templatesJan Beulich2024-09-262-349/+339
* x86: templatize SIMD FP arithmetic templatesJan Beulich2024-09-262-1135/+1100
* x86/APX: Don't promote AVX/AVX2 instructions out of APX specH.J. Lu2024-09-182-337/+197
* s390: Relax risbg[n]z, risb{h|l}gz, {rns|ros|rxs}bgt operand constraintsJens Remus2024-09-121-15/+9
* s390: Simplify (dis)assembly of insn operands with const bitsJens Remus2024-09-122-23/+17
* x86/APX: correct disassembly for EVEX.B4Jan Beulich2024-09-111-2/+3
* s390: Align opcodes to lower-caseJens Remus2024-09-091-1/+1
* x86/APX: use D for 2-operand CFCMOVccJan Beulich2024-09-062-577/+276
* x86/APX: optimize certain reg-only CFCMOVcc formsJan Beulich2024-09-062-31/+31
* x86: templatize VNNI templatesJan Beulich2024-09-062-46/+37
* RISC-V: Add support for XCVsimd extension in CV32E40PMary Bennett2024-09-032-0/+231
* Support ymm rounding control for Intel AVX10.2Haochen Jiang2024-09-026-629/+666
* x86/APX: drop %SW disassembler macro againJan Beulich2024-08-302-17/+19