diff options
| author |   Jan Beulich <jbeulich@suse.com> | 2024-11-18 11:45:34 +0100 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2024-11-18 11:45:34 +0100 |
| commit | 3c17b69fa1ac3b5c820caf5431532aa79e1e28cf (patch) | |
| tree | 12d11d1ef2d98c23827feaa8f3b7081f09c3ec1d /opcodes | |
| parent | [gdb/contrib] Fix spellcheck.sh for bash < 5.1 (diff) | |
| download | binutils-gdb-3c17b69fa1ac3b5c820caf5431532aa79e1e28cf.tar.gz binutils-gdb-3c17b69fa1ac3b5c820caf5431532aa79e1e28cf.tar.bz2 binutils-gdb-3c17b69fa1ac3b5c820caf5431532aa79e1e28cf.zip | |
x86: generalize "implicit quad group" handling
We'll want to re-use it for VP2INTERSECT{D,Q}.
While there add a testcase for the similarly affected AVX512-4VNNIW
insns.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/i386-opc.h | 8 | ||||
| -rw-r--r-- | opcodes/i386-opc.tbl | 14 |
2 files changed, 12 insertions, 10 deletions
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h index d404fbc6b05..4436ddc70f0 100644 --- a/opcodes/i386-opc.h +++ b/opcodes/i386-opc.h @@ -572,10 +572,12 @@ enum #define UGH 3 /* An implicit xmm0 as the first operand */ #define IMPLICIT_1ST_XMM0 4 - /* The second operand must be a vector register, {x,y,z}mmN, where N is a multiple of 4. - It implicitly denotes the register group of {x,y,z}mmN - {x,y,z}mm(N + 3). + /* One of the operands denotes a sequence of registers, with insn-dependent + constraint on the first register number. It implicitly denotes e.g. the + register group of {x,y,z}mmN - {x,y,z}mm(N + 3), in which case N ought to + be a multiple of 4. */ -#define IMPLICIT_QUAD_GROUP 5 +#define IMPLICIT_GROUP 5 /* Default mask isn't allowed. */ #define NO_DEFAULT_MASK 6 /* Address prefix changes register operand */ diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index b8be125ce56..90837b17a07 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -80,7 +80,7 @@ #define Anysize OperandConstraint=ANY_SIZE #define DistinctDest OperandConstraint=DISTINCT_DEST #define Implicit1stXmm0 OperandConstraint=IMPLICIT_1ST_XMM0 -#define ImplicitQuadGroup OperandConstraint=IMPLICIT_QUAD_GROUP +#define ImplicitGroup OperandConstraint=IMPLICIT_GROUP #define NoDefMask OperandConstraint=NO_DEFAULT_MASK #define RegKludge OperandConstraint=REG_KLUDGE #define Ugh OperandConstraint=UGH @@ -2879,17 +2879,17 @@ vpmultishiftqb, 0x6683, AVX512VBMI, Modrm|Masking|Space0F38|Src1VVVV|VexW1|Broad // AVX512_4FMAPS instructions -v4fmaddps, 0xf29a, AVX512_4FMAPS, Modrm|EVex=1|Masking|Space0F38|Src1VVVV|VexW0|Disp8MemShift=4|NoSuf|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex, RegZMM, RegZMM } -v4fnmaddps, 0xf2aa, AVX512_4FMAPS, Modrm|EVex=1|Masking|Space0F38|Src1VVVV|VexW0|Disp8MemShift=4|NoSuf|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex, RegZMM, RegZMM } -v4fmaddss, 0xf29b, AVX512_4FMAPS, Modrm|EVex=4|Masking|Space0F38|Src1VVVV|VexW0|Disp8MemShift=4|NoSuf|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex, RegXMM, RegXMM } -v4fnmaddss, 0xf2ab, AVX512_4FMAPS, Modrm|EVex=4|Masking|Space0F38|Src1VVVV|VexW0|Disp8MemShift=4|NoSuf|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex, RegXMM, RegXMM } +v4fmaddps, 0xf29a, AVX512_4FMAPS, Modrm|EVex=1|Masking|Space0F38|Src1VVVV|VexW0|Disp8MemShift=4|NoSuf|ImplicitGroup, { XMMword|Unspecified|BaseIndex, RegZMM, RegZMM } +v4fnmaddps, 0xf2aa, AVX512_4FMAPS, Modrm|EVex=1|Masking|Space0F38|Src1VVVV|VexW0|Disp8MemShift=4|NoSuf|ImplicitGroup, { XMMword|Unspecified|BaseIndex, RegZMM, RegZMM } +v4fmaddss, 0xf29b, AVX512_4FMAPS, Modrm|EVex=4|Masking|Space0F38|Src1VVVV|VexW0|Disp8MemShift=4|NoSuf|ImplicitGroup, { XMMword|Unspecified|BaseIndex, RegXMM, RegXMM } +v4fnmaddss, 0xf2ab, AVX512_4FMAPS, Modrm|EVex=4|Masking|Space0F38|Src1VVVV|VexW0|Disp8MemShift=4|NoSuf|ImplicitGroup, { XMMword|Unspecified|BaseIndex, RegXMM, RegXMM } // AVX512_4FMAPS instructions end // AVX512_4VNNIW instructions -vp4dpwssd, 0xf252, AVX512_4VNNIW, Modrm|EVex=1|Masking|Space0F38|Src1VVVV|VexW0|Disp8MemShift=4|NoSuf|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex, RegZMM, RegZMM } -vp4dpwssds, 0xf253, AVX512_4VNNIW, Modrm|EVex=1|Masking|Space0F38|Src1VVVV|VexW0|Disp8MemShift=4|NoSuf|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex, RegZMM, RegZMM } +vp4dpwssd, 0xf252, AVX512_4VNNIW, Modrm|EVex=1|Masking|Space0F38|Src1VVVV|VexW0|Disp8MemShift=4|NoSuf|ImplicitGroup, { XMMword|Unspecified|BaseIndex, RegZMM, RegZMM } +vp4dpwssds, 0xf253, AVX512_4VNNIW, Modrm|EVex=1|Masking|Space0F38|Src1VVVV|VexW0|Disp8MemShift=4|NoSuf|ImplicitGroup, { XMMword|Unspecified|BaseIndex, RegZMM, RegZMM } // AVX512_4VNNIW instructions end |