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* Add RXv3 instructions.Yoshinori Sato2019-01-133-1569/+5442
* S12Z: Don't crash when disassembling invalid instructions.John Darrington2019-01-092-3/+5
* S12Z: Fix disassembly of indexed OPR operands with zero index.John Darrington2019-01-092-30/+32
* Adjust bfd/warning.m4 egrep patternsAndrew Paprocki2019-01-092-5/+9
* s12z regenAlan Modra2019-01-073-3/+9
* S12Z: opcodes: Separate the decoding of operations from their display.John Darrington2019-01-038-2548/+3241
* Update year range in copyright notice of binutils filesAlan Modra2019-01-01269-272/+276
* ChangeLog rotationAlan Modra2019-01-012-2538/+2552
* PR24028, PPC_INT_FMTAlan Modra2018-12-282-10/+16
* Include bfd_stdint.h in bfd.hAlan Modra2018-12-188-6/+17
* RISC-V: Fix 4-arg add parsing.Jim Wilson2018-12-072-1/+6
* sim/opcodes: Allow use of out of tree cgen source directoryAndrew Burgess2018-12-063-8/+26
* opcodes/riscv: Hide '.L0 ' fake symbolsAndrew Burgess2018-12-063-0/+28
* RISC-V: Accept version, supervisor ext and more than one NSE for -march.Jim Wilson2018-12-032-1/+6
* [aarch64] - Only use MOV for disassembly when shifter op is LSL #0Egeyar Bagcioglu2018-12-032-1/+8
* RISC-V: Add missing c.unimp instruction.Jim Wilson2018-11-292-1/+7
* RISC-V: Add .insn CA support.Jim Wilson2018-11-272-2/+12
* S12Z opcodes: Fix bug disassembling certain shift instructions.John Darrington2018-11-212-19/+30
* opcodes/nfp: Fix disassembly of crc[] with swapped operands.Francois H. Theron2018-11-132-6/+10
* [BINUTILS, AARCH64, 8/8] Add data cache instructions for Memory Tagging Exten...Sudakshina Das2018-11-122-0/+48
* [BINUTILS, AARCH64, 7/8] Add system registers for Memory Tagging ExtensionSudakshina Das2018-11-122-0/+35
* [BINUTILS, AARCH64, 6/8] Add Tag getting instruction in Memory Tagging ExtensionSudakshina Das2018-11-1210-1642/+1724
* [BINUTILS, AARCH64, 5/8] Add Tag getting instruction in Memory Tagging ExtensionSudakshina Das2018-11-125-1607/+1633
* [BINUTILS, AARCH64, 4/8] Add Tag setting instructions in Memory Tagging Exten...Sudakshina Das2018-11-128-1841/+2036
* [BINUTILS, AARCH64, 3/8] Add Pointer Arithmetic instructions in Memory Taggin...Sudakshina Das2018-11-125-1904/+1942
* [BINUTILS, AARCH64, 2/8] Add Tag generation instructions in Memory Tagging Ex...Sudakshina Das2018-11-129-2913/+3010
* [BINUTILS, AARCH64, 1/8] Add support for Memory Tagging Extension for ARMv8.5-ASudakshina Das2018-11-122-0/+10
* [BINUTILS, ARM] Add Armv8.5-A to select_arm_features and update macros.Sudakshina Das2018-11-062-5/+10
* PowerPC instruction mask checksAlan Modra2018-11-062-141/+72
* x86: correctly handle VPBROADCASTD with EVEX.W set outside of 64-bit modeJan Beulich2018-11-062-1/+6
* x86: correctly handle VMOVD with EVEX.W set outside of 64-bit modeJan Beulich2018-11-063-14/+8
* x86: correctly handle KMOVD with VEX.W set outside of 64-bit modeJan Beulich2018-11-062-32/+17
* x86: adjust {,E}VEX.W handling for PEXTR* / PINSR*Jan Beulich2018-11-065-62/+47
* x86: adjust {,E}VEX.W handling outside of 64-bit modeJan Beulich2018-11-063-32/+39
* x86: fix various non-LIG templatesJan Beulich2018-11-063-86/+106
* x86: allow {store} to select alternative {,}PEXTRW encodingJan Beulich2018-11-063-11/+16
* x86: add more VexWIGJan Beulich2018-11-063-285/+293
* x86: XOP VPHADD* / VPHSUB* are VEX.W0Jan Beulich2018-11-063-32/+40
* S/390: Support vector alignment hintsAndreas Krebbel2018-10-231-0/+7
* S12Z: Disassembly: Fallback to show the address if the symbol table is empty.John Darrington2018-10-222-0/+9
* Arm: Fix disassembler crashing on -b binary when thumb file and thumb not for...Tamar Christina2018-10-192-3/+14
* AArch64: Fix error checking for SIMD udot (by element)Matthew Malcomson2018-10-162-1/+7
* x86: fold Size{16,32,64} template attributesJan Beulich2018-10-105-15577/+11696
* [PATCH, BINUTULS, AARCH64, 9/9] Add SSBS to MSR/MRSSudakshina Das2018-10-092-0/+23
* [PATCH, BINUTILS, AARCH64, 8/9] Add SCXTNUM_ELx and ID_PFR2_EL1 system registersSudakshina Das2018-10-092-0/+26
* [PATCH, BINUTILS, AARCH64, 7/9] Add BTI instructionSudakshina Das2018-10-098-1136/+1182
* [PATCH, BINUTILS, AARCH64, 6/9] Add Random number instructionsSudakshina Das2018-10-092-0/+16
* [PATCH, BINUTILS, AARCH64, 5/9] Add DC CVADP instructionSudakshina Das2018-10-092-0/+11
* [PATCH, BINUTILS, AARCH64, 4/9] Add Execution and Data Restriction instructionsSudakshina Das2018-10-097-1089/+1147
* [PATCH, BINUTILS, AARCH64, 3/9] Add instruction SB for ARMv8.5-ASudakshina Das2018-10-095-1014/+1030