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| author |   Tamar Christina <tamar.christina@arm.com> | 2018-10-03 18:37:07 +0100 |
|---|---|---|
| committer | Tamar Christina <tamar.christina@arm.com> | 2018-10-03 18:40:48 +0100 |
| commit | 755b748fd9fbee8cad2e55535d23298e8ac76b15 (patch) | |
| tree | b70510477152c03244207ba779875866c061c3da /opcodes | |
| parent | AArch64: Refactor err_type. (diff) | |
| download | binutils-gdb-755b748fd9fbee8cad2e55535d23298e8ac76b15.tar.gz binutils-gdb-755b748fd9fbee8cad2e55535d23298e8ac76b15.tar.bz2 binutils-gdb-755b748fd9fbee8cad2e55535d23298e8ac76b15.zip | |
AArch64: Refactor verifiers to make more general.
The current verifiers only take an instruction description and encoded value as
arguments. This was enough when the verifiers only needed to do simple checking
but it's insufficient for the purposes of validating instruction sequences.
This patch adds the required arguments and also a flag to allow a verifier to
distinguish between whether it's being run during encoding or decoding. It also
allows for errors and warnings to be returned by a verifier instead of a simple
pass/fail.
include/
* opcode/aarch64.h (struct aarch64_opcode): Expand verifiers to take
more arguments.
opcodes/
* aarch64-dis.c (aarch64_opcode_decode): Update verifier call.
* aarch64-opc.c (verify_ldpsw): Update arguments.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 5 | ||||
| -rw-r--r-- | opcodes/aarch64-dis.c | 3 | ||||
| -rw-r--r-- | opcodes/aarch64-opc.c | 15 |
3 files changed, 16 insertions, 7 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 1da4e80335c..aae54593ff0 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,5 +1,10 @@ 2018-10-03 Tamar Christina <tamar.christina@arm.com> + * aarch64-dis.c (aarch64_opcode_decode): Update verifier call. + * aarch64-opc.c (verify_ldpsw): Update arguments. + +2018-10-03 Tamar Christina <tamar.christina@arm.com> + * aarch64-dis.c (ERR_OK, ERR_UND, ERR_UNP, ERR_NYI): Remove. (aarch64_decode_insn, print_insn_aarch64_word): Use err_type. diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c index c08c82fb995..373ddae8a12 100644 --- a/opcodes/aarch64-dis.c +++ b/opcodes/aarch64-dis.c @@ -2885,7 +2885,8 @@ aarch64_opcode_decode (const aarch64_opcode *opcode, const aarch64_insn code, } /* If the opcode has a verifier, then check it now. */ - if (opcode->verifier && ! opcode->verifier (opcode, code)) + if (opcode->verifier + && opcode->verifier (inst, code, 0, FALSE, errors, NULL) != ERR_OK) { DEBUG_TRACE ("operand verifier FAIL"); goto decode_fail; diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index ba2af7bfc26..f35f0d692d3 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -4486,9 +4486,12 @@ aarch64_sys_ins_reg_supported_p (const aarch64_feature_set features, #define BIT(INSN,BT) (((INSN) >> (BT)) & 1) #define BITS(INSN,HI,LO) (((INSN) >> (LO)) & ((1 << (((HI) - (LO)) + 1)) - 1)) -static bfd_boolean -verify_ldpsw (const struct aarch64_opcode * opcode ATTRIBUTE_UNUSED, - const aarch64_insn insn) +static enum err_type +verify_ldpsw (const struct aarch64_inst *inst ATTRIBUTE_UNUSED, + const aarch64_insn insn, bfd_vma pc ATTRIBUTE_UNUSED, + bfd_boolean encoding ATTRIBUTE_UNUSED, + aarch64_operand_error *mismatch_detail ATTRIBUTE_UNUSED, + aarch64_instr_sequence *insn_block ATTRIBUTE_UNUSED) { int t = BITS (insn, 4, 0); int n = BITS (insn, 9, 5); @@ -4498,17 +4501,17 @@ verify_ldpsw (const struct aarch64_opcode * opcode ATTRIBUTE_UNUSED, { /* Write back enabled. */ if ((t == n || t2 == n) && n != 31) - return FALSE; + return ERR_UND; } if (BIT (insn, 22)) { /* Load */ if (t == t2) - return FALSE; + return ERR_UND; } - return TRUE; + return ERR_OK; } /* Return true if VALUE cannot be moved into an SVE register using DUP |