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path: root/opcodes/mips-opc.c
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* MIPS/opcodes: Mark MT thread context move assembly idioms as aliasesMaciej W. Rozycki2024-07-191-38/+38
* MIPS/opcodes: Mark PAUSE as an aliasMaciej W. Rozycki2024-07-191-1/+1
* MIPS/opcodes: Reorder coprocessor moves alphabeticallyMaciej W. Rozycki2024-07-191-48/+52
* MIPS/opcodes: Make AL a shorthand for INSN2_ALIASMaciej W. Rozycki2024-07-191-34/+36
* MIPS/opcodes: Rename the AL membership shorthand to ALXMaciej W. Rozycki2024-07-191-88/+88
* MIPS/opcodes: Remove the regular MIPS "+t" operand codeYunQiang Su2024-07-191-2/+1
* MIPS/opcodes: Output thread context registers numerically with MFTR/MTTRMaciej W. Rozycki2024-07-191-2/+2
* MIPS/opcodes: Exclude $0 from "-x" R6 operand typeMaciej W. Rozycki2024-07-191-1/+1
* MIPS/opcodes: Add MIPS Allegrex DBREAK instructionDavid Guillen Fandos2024-06-111-1/+1
* MIPS/opcodes: Exclude trap instructions for MIPS AllegrexDavid Guillen Fandos2024-06-111-30/+30
* Revert "MIPS/Allegrex: Exclude trap instructions"Maciej W. Rozycki2024-06-101-30/+30
* Revert "MIPS/Allegrex: Enable dbreak instruction"Maciej W. Rozycki2024-06-101-1/+1
* MIPS/Allegrex: Enable dbreak instructionDavid Guillen Fandos2024-06-101-1/+1
* MIPS/Allegrex: Exclude trap instructionsDavid Guillen Fandos2024-06-101-30/+30
* Update year range in copyright notice of binutils filesAlan Modra2024-01-041-1/+1
* Add additional missing Allegrex CPU instructionsDavid Guillen Fandos2023-06-151-14/+24
* Add rotation instructions to MIPS Allegrex CPUDavid Guillen Fandos2023-06-151-7/+7
* Add MIPS Allegrex CPU as a MIPS2-based CPUDavid Guillen Fandos2023-06-151-26/+29
* Revert "MIPS: sync oprand char usage between mips and micromips"Maciej W. Rozycki2023-06-151-18/+10
* MIPS: sync oprand char usage between mips and micromipsYunQiang Su2023-06-051-10/+18
* Update year range in copyright notice of binutils filesAlan Modra2023-01-011-1/+1
* MIPS/opcodes: Fix alias annotation for branch instructionsMaciej W. Rozycki2022-03-061-5/+6
* Update year range in copyright notice of binutils filesAlan Modra2022-01-021-1/+1
* MIPS/opcodes: Reorder legacy COP0, COP2, COP3 opcode instructionsMaciej W. Rozycki2021-05-291-66/+68
* MIPS/opcodes: Accurately record coprocessor opcode CPU/ISA membershipMaciej W. Rozycki2021-05-291-51/+51
* MIPS/opcodes: Remove DMFC3 and DMTC3 instructionsMaciej W. Rozycki2021-05-291-4/+0
* MIPS/opcodes: Disassemble the RFE instructionMaciej W. Rozycki2021-05-291-2/+3
* MIPS/opcodes: Do not use CP0 register names for control registersMaciej W. Rozycki2021-05-291-12/+14
* MIPS/opcodes: Free up redundant `g' operand codeMaciej W. Rozycki2021-05-291-4/+3
* Use bool in opcodesAlan Modra2021-03-311-22/+22
* Update year range in copyright notice of binutils filesAlan Modra2021-01-011-1/+1
* Update year range in copyright notice of binutils filesAlan Modra2020-01-011-1/+1
* MIPS/gas: Reject $0 as source register for DAUI instructionFaraz Shahbazker2019-05-211-1/+1
* Add macro expansions for ADD, SUB, DADD and DSUB for MIPS r6Faraz Shahbazker2019-05-101-4/+4
* Add load-link, store-conditional paired EVA instructionsFaraz Shahbazker2019-05-061-0/+5
* [MIPS] Add load-link, store-conditional paired instructionsAndrew Bennett2019-04-261-0/+8
* [MIPS] Add RDHWR with the SEL field for MIPS R6.Robert Suchanek2019-04-091-0/+1
* Update year range in copyright notice of binutils filesAlan Modra2019-01-011-1/+1
* [MIPS] Add Loongson 3A1000 proccessor support.Chenghua Xu2018-08-291-1/+1
* [MIPS/GAS] Add Loongson EXT2 Instructions support.Chenghua Xu2018-08-291-0/+7
* [MIPS/GAS] Split Loongson EXT Instructions from loongson3a.Chenghua Xu2018-08-291-64/+66
* [MIPS/GAS] Split Loongson CAM Instructions from loongson3aChenghua Xu2018-08-291-4/+7
* MIPS/GAS: Split Loongson MMI Instructions from loongson2f/3aChenghua Xu2018-07-201-80/+83
* MIPS: Add Global INValidate ASE supportFaraz Shahbazker2018-06-141-0/+8
* MIPS: Add CRC ASE supportScott Egerton2018-06-131-0/+14
* MIPS: Fix encoding for MIPSr6 sigrie instruction.Henry Wong2018-02-121-1/+1
* Update year range in copyright notice of binutils filesAlan Modra2018-01-031-1/+1
* MIPS/opcodes: Reorder LSA and DLSA instructionsMaciej W. Rozycki2017-06-301-3/+3
* MIPS: Fix XPA base and Virtualization ASE instruction handlingMaciej W. Rozycki2017-06-301-8/+9
* MIPS: Add Imagination interAptiv MR2 MIPS32r3 processor supportMaciej W. Rozycki2017-06-281-0/+11