diff options
Diffstat (limited to 'metadata/md5-cache/sci-electronics/iverilog-12.0')
| -rw-r--r-- | metadata/md5-cache/sci-electronics/iverilog-12.0 | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/metadata/md5-cache/sci-electronics/iverilog-12.0 b/metadata/md5-cache/sci-electronics/iverilog-12.0 index 0e3d389d6fb7..9aeb40c8de63 100644 --- a/metadata/md5-cache/sci-electronics/iverilog-12.0 +++ b/metadata/md5-cache/sci-electronics/iverilog-12.0 @@ -1,4 +1,4 @@ -BDEPEND=dev-util/gperf app-alternatives/yacc app-alternatives/lex >=app-portage/elt-patches-20240116 sys-devel/gnuconfig || ( >=dev-build/automake-1.17:1.17 >=dev-build/automake-1.16.5:1.16 ) || ( >=dev-build/autoconf-2.72-r1:2.72 >=dev-build/autoconf-2.71-r6:2.71 ) >=dev-build/libtool-2.4.7-r3 +BDEPEND=dev-util/gperf app-alternatives/yacc app-alternatives/lex >=app-portage/elt-patches-20240116 sys-devel/gnuconfig || ( >=dev-build/automake-1.17-r1:1.17 >=dev-build/automake-1.16.5:1.16 ) || ( >=dev-build/autoconf-2.72-r1:2.72 >=dev-build/autoconf-2.71-r6:2.71 ) >=dev-build/libtool-2.4.7-r3 DEFINED_PHASES=install prepare DEPEND=sys-libs/readline:= sys-libs/zlib DESCRIPTION=A Verilog simulation and synthesis tool @@ -10,5 +10,5 @@ LICENSE=LGPL-2.1 RDEPEND=sys-libs/readline:= sys-libs/zlib SLOT=0 SRC_URI=https://github.com/steveicarus/iverilog/archive/v12_0.tar.gz -> iverilog-12.0.tar.gz -_eclasses_=gnuconfig a397adda6984a4c423e28ac274c1ba98 toolchain-funcs e56c7649b804f051623c8bc1a1c44084 multilib c19072c3cd7ac5cb21de013f7e9832e0 libtool 5f49a16f67f81bdf873e3d1f10b10001 autotools fb7c3cd829c27448f5a05212de2bf499 +_eclasses_=gnuconfig a397adda6984a4c423e28ac274c1ba98 toolchain-funcs e56c7649b804f051623c8bc1a1c44084 multilib c19072c3cd7ac5cb21de013f7e9832e0 libtool 5f49a16f67f81bdf873e3d1f10b10001 autotools d12ccbad07b44642a75ac97a3334d8e0 _md5_=31b75f7824659041a2465eee094225b7 |