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author | Huang Rui <vowstar@gmail.com> | 2022-09-06 11:08:54 +0800 |
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committer | Huang Rui <vowstar@gmail.com> | 2022-09-06 11:08:54 +0800 |
commit | a616d5a11f134645da44e8463e655d0b3bc709ae (patch) | |
tree | ae813ebb420087bb6248717ca81a273966690a19 /sci-electronics | |
parent | sys-process/nvtop: fix 9999 ebuild (diff) | |
download | guru-a616d5a11f134645da44e8463e655d0b3bc709ae.tar.gz guru-a616d5a11f134645da44e8463e655d0b3bc709ae.tar.bz2 guru-a616d5a11f134645da44e8463e655d0b3bc709ae.zip |
sci-electronics/verilator: add 4.226
Signed-off-by: Huang Rui <vowstar@gmail.com>
Diffstat (limited to 'sci-electronics')
-rw-r--r-- | sci-electronics/verilator/Manifest | 1 | ||||
-rw-r--r-- | sci-electronics/verilator/verilator-4.226.ebuild | 42 |
2 files changed, 43 insertions, 0 deletions
diff --git a/sci-electronics/verilator/Manifest b/sci-electronics/verilator/Manifest index d8c3fce88..18e3fa597 100644 --- a/sci-electronics/verilator/Manifest +++ b/sci-electronics/verilator/Manifest @@ -1 +1,2 @@ DIST verilator-4.224.tar.gz 2574010 BLAKE2B 470e8f29044e9ed7356b236a9a8da4d36eb9b51b8d358edc44a6c41c4339c256a3ff883f07826ec18fa5acda3fe0933073615090f6c061f80379d0713da239d1 SHA512 a2a37948878ad897668ce89b0f12978dcbda3726cebb134db6ff6f172573d4e488748699a84008359d808d5b6fad19c013edaebc7f8a24a5452b61b1d57dc283 +DIST verilator-4.226.tar.gz 2605577 BLAKE2B 2a93e7bcbf9c87baca97e887b7460e4735fb60809b2cf636a7a235b07c7528667ec2586e2bd405aeb7b247028f2ea09a75861305aefe0d05b9e779f7c23686c4 SHA512 bede9024f45491884533929aa04705908aaf9fda5848a8ee7ca865569b2e5c9267ba20d8e140e67d86f322f7c7cf6d4562014f00e826ec69c8c39a3a3644c5c3 diff --git a/sci-electronics/verilator/verilator-4.226.ebuild b/sci-electronics/verilator/verilator-4.226.ebuild new file mode 100644 index 000000000..2c41dd1ed --- /dev/null +++ b/sci-electronics/verilator/verilator-4.226.ebuild @@ -0,0 +1,42 @@ +# Copyright 1999-2022 Gentoo Authors +# Distributed under the terms of the GNU General Public License v2 + +EAPI="8" + +inherit autotools + +DESCRIPTION="The fast free Verilog/SystemVerilog simulator" +HOMEPAGE=" + https://verilator.org + https://github.com/verilator/verilator +" + +if [[ "${PV}" == "9999" ]] ; then + inherit git-r3 + EGIT_REPO_URI="https://github.com/${PN}/${PN}.git" +else + SRC_URI="https://github.com/${PN}/${PN}/archive/v${PV}.tar.gz -> ${P}.tar.gz" + KEYWORDS="~alpha ~amd64 ~arm ~arm64 ~hppa ~ia64 ~m68k ~mips ~ppc ~ppc64 ~riscv ~s390 ~sparc ~x86" +fi + +LICENSE="|| ( Artistic-2 LGPL-3 )" +SLOT="0" + +RDEPEND=" + dev-lang/perl + sys-libs/zlib +" + +DEPEND=" + ${RDEPEND} +" + +BDEPEND=" + sys-devel/bison + sys-devel/flex +" + +src_prepare() { + default + eautoconf --force +} |