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path: root/include/opcode/mips.h
Commit message (Expand)AuthorAgeFilesLines
* MIPS/opcodes: Rework documentation for instruction argsMaciej W. Rozycki2024-09-151-400/+402
* microMIPS: Add MT ASE instruction set supportYunQiang Su2024-07-261-3/+11
* MIPS/opcodes: Replace "y" microMIPS operand code with "x"Maciej W. Rozycki2024-07-191-2/+2
* MIPS/opcodes: Remove the regular MIPS "+t" operand codeYunQiang Su2024-07-191-2/+1
* MIPS/opcodes: Discard unused OP_SH, OP_MASK, and OP_OP macrosMaciej W. Rozycki2024-07-191-454/+0
* MIPS/opcodes: Correct documentation for R6 operand typesMaciej W. Rozycki2024-07-191-7/+6
* MIPS/opcodes: Rework INSN_* flags into a consistent blockMaciej W. Rozycki2024-06-131-28/+25
* MIPS/opcodes: Update INSN_CHIP_MASK for INSN_ALLEGREXMaciej W. Rozycki2024-06-131-1/+1
* Update year range in copyright notice of binutils filesAlan Modra2024-01-041-1/+1
* Add MIPS Allegrex CPU as a MIPS2-based CPUDavid Guillen Fandos2023-06-151-0/+6
* Revert "MIPS: add MT ASE support for micromips32"Maciej W. Rozycki2023-06-151-25/+10
* Revert "MIPS: sync oprand char usage between mips and micromips"Maciej W. Rozycki2023-06-151-12/+2
* MIPS: sync oprand char usage between mips and micromipsYunQiang Su2023-06-051-2/+12
* MIPS: add MT ASE support for micromips32YunQiang Su2023-06-051-10/+25
* Update year range in copyright notice of binutils filesAlan Modra2023-01-011-1/+1
* Update year range in copyright notice of binutils filesAlan Modra2022-01-021-1/+1
* MIPS/opcodes: Properly handle ISA exclusionMaciej W. Rozycki2021-05-291-19/+18
* MIPS/opcodes: Factor out ISA matching against flagsMaciej W. Rozycki2021-05-291-4/+21
* MIPS/opcodes: Do not use CP0 register names for control registersMaciej W. Rozycki2021-05-291-2/+9
* MIPS/opcodes: Free up redundant `g' operand codeMaciej W. Rozycki2021-05-291-2/+1
* Use bool in includeAlan Modra2021-03-311-17/+17
* Update year range in copyright notice of binutils filesAlan Modra2021-01-011-1/+1
* Update year range in copyright notice of binutils filesAlan Modra2020-01-011-1/+1
* Add load-link, store-conditional paired EVA instructionsFaraz Shahbazker2019-05-061-0/+5
* [MIPS] Add load-link, store-conditional paired instructionsAndrew Bennett2019-04-261-0/+4
* MIPS/include: opcode/mips.h: Update stale comment for CODE20 operandMaciej W. Rozycki2019-04-251-2/+2
* Update year range in copyright notice of binutils filesAlan Modra2019-01-011-1/+1
* [MIPS] Add Loongson 2K1000 proccessor support.Chenghua Xu2018-08-291-0/+1
* [MIPS] Add Loongson 3A2000/3A3000 proccessor support.Chenghua Xu2018-08-291-0/+1
* [MIPS] Add Loongson 3A1000 proccessor support.Chenghua Xu2018-08-291-7/+2
* [MIPS/GAS] Add Loongson EXT2 Instructions support.Chenghua Xu2018-08-291-0/+2
* [MIPS/GAS] Split Loongson EXT Instructions from loongson3a.Chenghua Xu2018-08-291-0/+2
* [MIPS/GAS] Split Loongson CAM Instructions from loongson3aChenghua Xu2018-08-291-0/+2
* MIPS/GAS: Split Loongson MMI Instructions from loongson2f/3aChenghua Xu2018-07-201-0/+2
* MIPS: Add Global INValidate ASE supportFaraz Shahbazker2018-06-141-1/+6
* MIPS: Add CRC ASE supportScott Egerton2018-06-131-0/+3
* MIPS16/opcodes: Free up `M' operand codeMaciej W. Rozycki2018-02-201-3/+2
* Update year range in copyright notice of binutils filesAlan Modra2018-01-031-1/+1
* MIPS: Fix XPA base and Virtualization ASE instruction handlingMaciej W. Rozycki2017-06-301-0/+3
* MIPS: Add Imagination interAptiv MR2 MIPS32r3 processor supportMaciej W. Rozycki2017-06-281-5/+16
* MIPS16e2: Add MIPS16e2 ASE supportMaciej W. Rozycki2017-05-151-5/+34
* Update year range in copyright notice of all files.Alan Modra2017-01-021-1/+1
* MIPS16: Add ASMACRO instruction supportMaciej W. Rozycki2016-12-231-2/+8
* MIPS16: Reassign `0' and `4' operand codesMaciej W. Rozycki2016-12-231-5/+5
* MIPS16: Handle non-extensible instructions correctlyMaciej W. Rozycki2016-12-231-0/+4
* MIPS16: Switch to 32-bit opcode table interpretationMaciej W. Rozycki2016-12-201-0/+8
* MIPS16: Remove unused `>' operand codeMaciej W. Rozycki2016-12-091-2/+1
* MIPS/include: opcode/mips.h: Correct INSN_CHIP_MASKMaciej W. Rozycki2016-12-071-1/+1
* MIPS/include: opcode/mips.h: Add a comment for ASE_DSPR3Maciej W. Rozycki2016-12-071-0/+1
* add more extern CTrevor Saunders2016-06-011-0/+8