x86-64: accept 64-bit LFS/LGS/LSS forms with suffix or operand size specifier

Since we accept these without suffix / operand size specifier, we should
also do so with one. (The fact that we unilaterally accept these, other
than far branches, rather than limiting them to Intel64 mode, will be
taken care of later on.)

Also take the opportunity and make sure "lfs <reg>, tbyte ptr <mem>"
et al get rejected outside of 64-bit mode. This became broken by
dc2be329b950 ("i386: Only check suffix in instruction mnemonic").
Furthermore cover lgdt et al in the Intel syntax handling as well, which
continued to work after said commit just by coincidence.

9 files changed, 90 insertions, 8 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index d309806521e..992be9bbe3c 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,19 @@
 2019-12-04  Jan Beulich  <jbeulich@suse.com>
 
+	* config/tc-i386-intel.c (i386_intel_operand): Handle LFS et al
+	as well as LGDT at al when processing O_tbyte_ptr.
+	* testsuite/gas/i386/intelbad.s: Add LDS et al cases.
+	* testsuite/gas/i386/x86-64-intel64.s,
+	* testsuite/gas/i386/x86-64-opcode.s:  Add LFS et al cases.
+	* testsuite/gas/i386/ilp32/x86-64-intel64.d: Add -mintel64
+	command line option and fold expectations with parent dir test.
+	* testsuite/gas/i386/x86-64-intel64.d: Add -mintel64 command
+	line option and adjust expectations.
+	* testsuite/gas/i386/intelbad.l,
+	testsuite/gas/i386/x86-64-opcode.d: Adjust expectations.
+
+2019-12-04  Jan Beulich  <jbeulich@suse.com>
+
 	* config/tc-i386-intel.c (i386_intel_operand): Also handle DWORD
 	with 64-bit mode branches.
 	* testsuite/gas/i386/x86-64-jump.s: Extend Intel syntax branch
diff --git a/gas/config/tc-i386-intel.c b/gas/config/tc-i386-intel.c
index 51fa38d91f6..b639ab7dd6b 100644
--- a/gas/config/tc-i386-intel.c
+++ b/gas/config/tc-i386-intel.c
@@ -698,6 +698,15 @@ i386_intel_operand (char *operand_string, int got_a_float)
 	  i.types[this_operand].bitfield.tbyte = 1;
 	  if (got_a_float == 1)
 	    suffix = LONG_DOUBLE_MNEM_SUFFIX;
+	  else if (current_templates->start->operand_types[0].bitfield.fword
+		   || current_templates->start->operand_types[0].bitfield.tbyte)
+	    {
+	      /* l[defgs]s, [ls][gi]dt */
+	      if (flag_code == CODE_64BIT)
+		suffix = QWORD_MNEM_SUFFIX;
+	      else
+		i.types[this_operand].bitfield.byte = 1; /* cause an error */
+	    }
 	  else
 	    suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
 	  break;
diff --git a/gas/testsuite/gas/i386/ilp32/x86-64-intel64.d b/gas/testsuite/gas/i386/ilp32/x86-64-intel64.d
index 74d863df43d..120e5670887 100644
--- a/gas/testsuite/gas/i386/ilp32/x86-64-intel64.d
+++ b/gas/testsuite/gas/i386/ilp32/x86-64-intel64.d
@@ -1,11 +1,5 @@
 #source: ../x86-64-intel64.s
+#as: -mintel64
 #objdump: -dw
 #name: x86-64 (ILP32) Intel64
-
-.*: +file format .*
-
-Disassembly of section .text:
-0+ <_start>:
-[ 	]*[a-f0-9]+:	0f 05                	syscall 
-[ 	]*[a-f0-9]+:	0f 07                	sysret 
-#pass
+#dump: ../x86-64-intel64.d
diff --git a/gas/testsuite/gas/i386/intelbad.l b/gas/testsuite/gas/i386/intelbad.l
index 6321cc8f867..4dc091741f6 100644
--- a/gas/testsuite/gas/i386/intelbad.l
+++ b/gas/testsuite/gas/i386/intelbad.l
@@ -152,3 +152,8 @@
 .*:168: Error: .*
 .*:169: Error: .*
 .*:172: Error: .*
+.*:174: Error: .*
+.*:175: Error: .*
+.*:176: Warning: .*
+.*:177: Error: .*
+.*:178: Error: .*
diff --git a/gas/testsuite/gas/i386/intelbad.s b/gas/testsuite/gas/i386/intelbad.s
index b3d1f76f81b..93e1c44e84b 100644
--- a/gas/testsuite/gas/i386/intelbad.s
+++ b/gas/testsuite/gas/i386/intelbad.s
@@ -170,3 +170,9 @@ start:
 #XXX?	movzx	eax, byte ptr [1]
 
 	mov	eax, 3:5
+
+	lds	eax, byte ptr [eax]
+	les	eax, word ptr [eax]
+	lfs	eax, dword ptr [eax]
+	lgs	eax, qword ptr [eax]
+	lss	eax, tbyte ptr [eax]
diff --git a/gas/testsuite/gas/i386/x86-64-intel64.d b/gas/testsuite/gas/i386/x86-64-intel64.d
index 13e723170e4..545fcdcfc54 100644
--- a/gas/testsuite/gas/i386/x86-64-intel64.d
+++ b/gas/testsuite/gas/i386/x86-64-intel64.d
@@ -1,3 +1,4 @@
+#as: -mintel64
 #objdump: -dw
 #name: x86-64 Intel64
 
@@ -5,6 +6,18 @@
 
 Disassembly of section .text:
 0+ <_start>:
+[ 	]*[a-f0-9]+:	48 0f b4 08          	lfs    \(%rax\),%rcx
+[ 	]*[a-f0-9]+:	48 0f b4 08          	lfs    \(%rax\),%rcx
+[ 	]*[a-f0-9]+:	48 0f b5 11          	lgs    \(%rcx\),%rdx
+[ 	]*[a-f0-9]+:	48 0f b5 11          	lgs    \(%rcx\),%rdx
+[ 	]*[a-f0-9]+:	48 0f b2 1a          	lss    \(%rdx\),%rbx
+[ 	]*[a-f0-9]+:	48 0f b2 1a          	lss    \(%rdx\),%rbx
 [ 	]*[a-f0-9]+:	0f 05                	syscall 
 [ 	]*[a-f0-9]+:	0f 07                	sysret 
+[ 	]*[a-f0-9]+:	48 0f b4 01          	lfs    \(%rcx\),%rax
+[ 	]*[a-f0-9]+:	48 0f b4 01          	lfs    \(%rcx\),%rax
+[ 	]*[a-f0-9]+:	48 0f b5 0a          	lgs    \(%rdx\),%rcx
+[ 	]*[a-f0-9]+:	48 0f b5 0a          	lgs    \(%rdx\),%rcx
+[ 	]*[a-f0-9]+:	48 0f b2 13          	lss    \(%rbx\),%rdx
+[ 	]*[a-f0-9]+:	48 0f b2 13          	lss    \(%rbx\),%rdx
 #pass
diff --git a/gas/testsuite/gas/i386/x86-64-intel64.s b/gas/testsuite/gas/i386/x86-64-intel64.s
index 1c2b45507ea..233f6b72a60 100644
--- a/gas/testsuite/gas/i386/x86-64-intel64.s
+++ b/gas/testsuite/gas/i386/x86-64-intel64.s
@@ -3,5 +3,20 @@
 	.text
 	.arch core2
 _start:
+	lfs	(%rax), %rcx
+	lfsq	(%rax), %rcx
+	lgs	(%rcx), %rdx
+	lgsq	(%rcx), %rdx
+	lss	(%rdx), %rbx
+	lssq	(%rdx), %rbx
+
 	syscall
 	sysret
+
+	.intel_syntax noprefix
+	lfs	rax, [rcx]
+	lfs	rax, tbyte ptr [rcx]
+	lgs	rcx, [rdx]
+	lgs	rcx, tbyte ptr [rdx]
+	lss	rdx, [rbx]
+	lss	rdx, tbyte ptr [rbx]
diff --git a/gas/testsuite/gas/i386/x86-64-opcode.d b/gas/testsuite/gas/i386/x86-64-opcode.d
index d8a1e44a451..70e40307f0b 100644
--- a/gas/testsuite/gas/i386/x86-64-opcode.d
+++ b/gas/testsuite/gas/i386/x86-64-opcode.d
@@ -45,6 +45,18 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	c7 00 00 00 00 70    	movl   \$0x70000000,\(%rax\)
 [ 	]*[a-f0-9]+:	49 c7 00 00 00 00 70 	movq   \$0x70000000,\(%r8\)
 [ 	]*[a-f0-9]+:	48 c7 00 00 00 00 70 	movq   \$0x70000000,\(%rax\)
+[ 	]*[a-f0-9]+:	0f b4 08             	lfs    \(%rax\),%ecx
+[ 	]*[a-f0-9]+:	0f b4 01             	lfs    \(%rcx\),%eax
+[ 	]*[a-f0-9]+:	66 0f b4 08          	lfs    \(%rax\),%cx
+[ 	]*[a-f0-9]+:	66 0f b4 01          	lfs    \(%rcx\),%ax
+[ 	]*[a-f0-9]+:	0f b5 11             	lgs    \(%rcx\),%edx
+[ 	]*[a-f0-9]+:	0f b5 0a             	lgs    \(%rdx\),%ecx
+[ 	]*[a-f0-9]+:	66 0f b5 11          	lgs    \(%rcx\),%dx
+[ 	]*[a-f0-9]+:	66 0f b5 0a          	lgs    \(%rdx\),%cx
+[ 	]*[a-f0-9]+:	0f b2 1a             	lss    \(%rdx\),%ebx
+[ 	]*[a-f0-9]+:	0f b2 13             	lss    \(%rbx\),%edx
+[ 	]*[a-f0-9]+:	66 0f b2 1a          	lss    \(%rdx\),%bx
+[ 	]*[a-f0-9]+:	66 0f b2 13          	lss    \(%rbx\),%dx
 [ 	]*[a-f0-9]+:	41 0f c3 00          	movnti %eax,\(%r8\)
 [ 	]*[a-f0-9]+:	0f c3 00             	movnti %eax,\(%rax\)
 [ 	]*[a-f0-9]+:	49 0f c3 00          	movnti %rax,\(%r8\)
diff --git a/gas/testsuite/gas/i386/x86-64-opcode.s b/gas/testsuite/gas/i386/x86-64-opcode.s
index caee124d160..f066e613bd3 100644
--- a/gas/testsuite/gas/i386/x86-64-opcode.s
+++ b/gas/testsuite/gas/i386/x86-64-opcode.s
@@ -50,6 +50,20 @@
 	MOVq $0x70000000,(%r8)	      # --  --  -- 49   C7 00 00 00 00 70		 ; REX for 64-bit operand size. REX to access upper reg.
 	MOVq $0x70000000,(%rax)	      # --  --  -- 48   C7 00 00 00 00 70		 ; REX for 64-bit operand size
 
+	# LFS etc
+	LFS  (%rax), %ecx             # --  --  -- --   0F B4 ..
+	LFSl (%rcx), %eax             # --  --  -- --   0F B4 ..
+	LFS  (%rax), %cx              # 66  --  -- --   0F B4 ..
+	LFSw (%rcx), %ax              # 66  --  -- --   0F B4 ..
+	LGS  (%rcx), %edx             # --  --  -- --   0F B5 ..
+	LGSl (%rdx), %ecx             # --  --  -- --   0F B5 ..
+	LGS  (%rcx), %dx              # 66  --  -- --   0F B5 ..
+	LGSw (%rdx), %cx              # 66  --  -- --   0F B5 ..
+	LSS  (%rdx), %ebx             # --  --  -- --   0F B2 ..
+	LSSl (%rbx), %edx             # --  --  -- --   0F B2 ..
+	LSS  (%rdx), %bx              # 66  --  -- --   0F B2 ..
+	LSSw (%rbx), %dx              # 66  --  -- --   0F B2 ..
+
 	# MOVNTI
 	MOVNTI %eax,(%r8)	      # --  --  -- 41   0f c3 00			 ; REX to access upper reg.
 	MOVNTI %eax,(%rax)	      # --  --  -- --   0f c3 00