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| author |   Jan Beulich <jbeulich@suse.com> | 2019-11-11 13:28:35 +0100 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2019-11-11 13:28:35 +0100 |
| commit | 91802f3cfed1524ebcfef1057afad4f98519ca78 (patch) | |
| tree | 3ed6ef5c73754fd451a015a5566a3a8a741b9038 | |
| parent | Arm64: fix build with old glibc (diff) | |
| download | binutils-gdb-91802f3cfed1524ebcfef1057afad4f98519ca78.tar.gz binutils-gdb-91802f3cfed1524ebcfef1057afad4f98519ca78.tar.bz2 binutils-gdb-91802f3cfed1524ebcfef1057afad4f98519ca78.zip | |
Arm64: SVE2's smaxp/sminp require operands 1 and 3 to be the same register
This is just like for their umaxp/uminp and fmaxp/fminp counterparts.
| -rw-r--r-- | gas/ChangeLog | 6 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/illegal-sve2.l | 2 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/illegal-sve2.s | 2 | ||||
| -rw-r--r-- | opcodes/ChangeLog | 5 | ||||
| -rw-r--r-- | opcodes/aarch64-tbl.h | 4 |
5 files changed, 17 insertions, 2 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index 29cf763df59..e59a6db76d4 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,9 @@ +2019-11-11 Jan Beulich <jbeulich@suse.com> + + * testsuite/gas/aarch64/illegal-sve2.s: Add smaxp/sminp cases + with mismatched 1st and 3rd operands. + * testsuite/gas/aarch64/illegal-sve2.l: Adjust expectations. + 2019-11-08 H.J. Lu <hongjiu.lu@intel.com> PR gas/25167 diff --git a/gas/testsuite/gas/aarch64/illegal-sve2.l b/gas/testsuite/gas/aarch64/illegal-sve2.l index 01c68479c4c..7656c2f91b1 100644 --- a/gas/testsuite/gas/aarch64/illegal-sve2.l +++ b/gas/testsuite/gas/aarch64/illegal-sve2.l @@ -1094,6 +1094,7 @@ [^ :]+:[0-9]+: Info: smaxp z0\.h, p0/m, z0\.h, z0\.h [^ :]+:[0-9]+: Info: smaxp z0\.s, p0/m, z0\.s, z0\.s [^ :]+:[0-9]+: Info: smaxp z0\.d, p0/m, z0\.d, z0\.d +[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `smaxp z1\.b,p0/m,z0\.b,z0\.b' [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `smaxp z32\.b,p0/m,z0\.b,z0\.b' [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `smaxp z0\.b,p0/m,z32\.b,z0\.b' [^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `smaxp z0\.b,p0/m,z0\.b,z32\.b' @@ -1112,6 +1113,7 @@ [^ :]+:[0-9]+: Info: sminp z0\.h, p0/m, z0\.h, z0\.h [^ :]+:[0-9]+: Info: sminp z0\.s, p0/m, z0\.s, z0\.s [^ :]+:[0-9]+: Info: sminp z0\.d, p0/m, z0\.d, z0\.d +[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `sminp z1\.b,p0/m,z0\.b,z0\.b' [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sminp z32\.b,p0/m,z0\.b,z0\.b' [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sminp z0\.b,p0/m,z32\.b,z0\.b' [^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `sminp z0\.b,p0/m,z0\.b,z32\.b' diff --git a/gas/testsuite/gas/aarch64/illegal-sve2.s b/gas/testsuite/gas/aarch64/illegal-sve2.s index c963a5c2710..8ad7fbf1d1b 100644 --- a/gas/testsuite/gas/aarch64/illegal-sve2.s +++ b/gas/testsuite/gas/aarch64/illegal-sve2.s @@ -720,6 +720,7 @@ sm4ekey z0.s, z0.s, z0.h smaxp z0.h, p0/m, z0.b, z0.b smaxp z0.b, p0/z, z0.b, z0.b +smaxp z1.b, p0/m, z0.b, z0.b smaxp z32.b, p0/m, z0.b, z0.b smaxp z0.b, p0/m, z32.b, z0.b smaxp z0.b, p0/m, z0.b, z32.b @@ -727,6 +728,7 @@ smaxp z0.b, p8/m, z0.b, z0.b sminp z0.h, p0/m, z0.b, z0.b sminp z0.b, p0/z, z0.b, z0.b +sminp z1.b, p0/m, z0.b, z0.b sminp z32.b, p0/m, z0.b, z0.b sminp z0.b, p0/m, z32.b, z0.b sminp z0.b, p0/m, z0.b, z32.b diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 1f9d4a545ea..ad1874c5d67 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,5 +1,10 @@ 2019-11-11 Jan Beulich <jbeulich@suse.com> + * aarch64-tbl.h (aarch64_opcode_table): Switch SVE2's + smaxp/sminp entries' "tied_operand" field to 2. + +2019-11-11 Jan Beulich <jbeulich@suse.com> + * aarch64-opc.c (operand_general_constraint_met_p): Replace "index" local variable by that of the already existing "num". diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index dc7661a9689..aa8b8b3f907 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -4805,8 +4805,8 @@ struct aarch64_opcode aarch64_opcode_table[] = SVE2_INSNC ("shsub", 0x44128000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zn), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), SVE2_INSNC ("shsubr", 0x44168000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zn), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), SVE2_INSN ("sli", 0x4500f400, 0xff20fc00, sve_shift_tsz_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_SHLIMM_UNPRED), OP_SVE_VVU_BHSD, 0, 0), - SVE2_INSNC ("smaxp", 0x4414a000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zn), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 0), - SVE2_INSNC ("sminp", 0x4416a000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zn), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 0), + SVE2_INSNC ("smaxp", 0x4414a000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zn), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), + SVE2_INSNC ("sminp", 0x4416a000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zn), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2), SVE2_INSNC ("smlalb", 0x44a08000, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0), SVE2_INSNC ("smlalb", 0x44e08000, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm4_11_INDEX), OP_SVE_DSS, 0, C_SCAN_MOVPRFX, 0), SVE2_INSNC ("smlalb", 0x44004000, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS, 0, C_SCAN_MOVPRFX, 0), |