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| author |   Denis Dupeyron <calchan@gentoo.org> | 2006-07-02 14:59:18 +0000 |
|---|---|---|
| committer | Denis Dupeyron <calchan@gentoo.org> | 2006-07-02 14:59:18 +0000 |
| commit | 824cfcd6a91cbf9c150c9f25877ca3ac6fe7b52b (patch) | |
| tree | b398d100ff0138a61a29a79ec75d3e0f8706b0bb /sci-electronics/modelsim | |
| parent | Stable on ppc; bug #138482. (diff) | |
| download | gentoo-2-824cfcd6a91cbf9c150c9f25877ca3ac6fe7b52b.tar.gz gentoo-2-824cfcd6a91cbf9c150c9f25877ca3ac6fe7b52b.tar.bz2 gentoo-2-824cfcd6a91cbf9c150c9f25877ca3ac6fe7b52b.zip | |
Adjusted metadata, see bug #138062.
(Portage version: 2.1.1_pre1-r5)
Diffstat (limited to 'sci-electronics/modelsim')
| -rw-r--r-- | sci-electronics/modelsim/ChangeLog | 7 | ||||
| -rw-r--r-- | sci-electronics/modelsim/metadata.xml | 7 |
2 files changed, 11 insertions, 3 deletions
diff --git a/sci-electronics/modelsim/ChangeLog b/sci-electronics/modelsim/ChangeLog index 18a4fa6706e2..d3d6890ab9df 100644 --- a/sci-electronics/modelsim/ChangeLog +++ b/sci-electronics/modelsim/ChangeLog @@ -1,6 +1,9 @@ # ChangeLog for sci-electronics/modelsim -# Copyright 2000-2004 Gentoo Foundation; Distributed under the GPL v2 -# $Header: /var/cvsroot/gentoo-x86/sci-electronics/modelsim/ChangeLog,v 1.2 2004/12/27 21:02:54 swegener Exp $ +# Copyright 2000-2006 Gentoo Foundation; Distributed under the GPL v2 +# $Header: /var/cvsroot/gentoo-x86/sci-electronics/modelsim/ChangeLog,v 1.3 2006/07/02 14:59:18 calchan Exp $ + + 02 Jul 2006; Denis Dupeyron <calchan@gentoo.org> metadata.xml: + Adjusted metadata, see bug #138062. *modelsim-5.7d (27 Dec 2004) diff --git a/sci-electronics/modelsim/metadata.xml b/sci-electronics/modelsim/metadata.xml index b229aec85b8f..e8fd19d7b0ae 100644 --- a/sci-electronics/modelsim/metadata.xml +++ b/sci-electronics/modelsim/metadata.xml @@ -1,5 +1,10 @@ <?xml version="1.0" encoding="UTF-8"?> <!DOCTYPE pkgmetadata SYSTEM "http://www.gentoo.org/dtd/metadata.dtd"> <pkgmetadata> -<herd>sci</herd> + <herd>sci-electronics</herd> + <longdescription> + ModelSim is a commercial tool providing a comprehensive simulation and debug + environment for complex ASIC and FPGA designs. Support is provided for + multiple languages including Verilog, SystemVerilog, VHDL and SystemC. + </longdescription> </pkgmetadata> |