diff options
Diffstat (limited to 'target-i386')
| -rw-r--r-- | target-i386/cpu.h | 24 | ||||
| -rw-r--r-- | target-i386/fake-exec.c | 50 | ||||
| -rw-r--r-- | target-i386/helper.c | 38 | ||||
| -rw-r--r-- | target-i386/kvm.c | 15 | ||||
| -rw-r--r-- | target-i386/libkvm.h | 28 | ||||
| -rw-r--r-- | target-i386/machine.c | 7 |
6 files changed, 149 insertions, 13 deletions
diff --git a/target-i386/cpu.h b/target-i386/cpu.h index 5929d2813..4605fd280 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -250,16 +250,32 @@ #define PG_ERROR_RSVD_MASK 0x08 #define PG_ERROR_I_D_MASK 0x10 -#define MCG_CTL_P (1UL<<8) /* MCG_CAP register available */ +#define MCG_CTL_P (1ULL<<8) /* MCG_CAP register available */ +#define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */ -#define MCE_CAP_DEF MCG_CTL_P +#define MCE_CAP_DEF (MCG_CTL_P|MCG_SER_P) #define MCE_BANKS_DEF 10 +#define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */ +#define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */ #define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */ #define MCI_STATUS_VAL (1ULL<<63) /* valid error */ #define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */ #define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */ +#define MCI_STATUS_EN (1ULL<<60) /* error enabled */ +#define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */ +#define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */ +#define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */ +#define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */ +#define MCI_STATUS_AR (1ULL<<55) /* Action required */ + +/* MISC register defines */ +#define MCM_ADDR_SEGOFF 0 /* segment offset */ +#define MCM_ADDR_LINEAR 1 /* linear address */ +#define MCM_ADDR_PHYS 2 /* physical address */ +#define MCM_ADDR_MEM 3 /* memory address */ +#define MCM_ADDR_GENERIC 7 /* generic */ #define MSR_IA32_TSC 0x10 #define MSR_IA32_APICBASE 0x1b @@ -651,6 +667,8 @@ typedef struct CPUX86State { target_ulong fmask; target_ulong kernelgsbase; #endif + uint64_t system_time_msr; + uint64_t wall_clock_msr; uint64_t tsc; @@ -870,7 +888,7 @@ uint64_t cpu_get_tsc(CPUX86State *env); #define cpu_signal_handler cpu_x86_signal_handler #define cpu_list x86_cpu_list -#define CPU_SAVE_VERSION 11 +#define CPU_SAVE_VERSION 12 /* MMU modes definitions */ #define MMU_MODE0_SUFFIX _kernel diff --git a/target-i386/fake-exec.c b/target-i386/fake-exec.c new file mode 100644 index 000000000..dfa202d6a --- /dev/null +++ b/target-i386/fake-exec.c @@ -0,0 +1,50 @@ +/* + * fake-exec.c + * + * This is a file for stub functions so that compilation is possible + * when TCG CPU emulation is disabled during compilation. + * + * Copyright 2007 IBM Corporation. + * Added by & Authors: + * Jerone Young <jyoung5@us.ibm.com> + * This work is licensed under the GNU GPL licence version 2 or later. + * + */ +#include "exec.h" +#include "cpu.h" + +int code_copy_enabled = 0; + +CCTable cc_table[CC_OP_NB]; + +void cpu_dump_statistics (CPUState *env, FILE*f, + int (*cpu_fprintf)(FILE *f, const char *fmt, ...), + int flags) +{ +} + +unsigned long code_gen_max_block_size(void) +{ + return 32; +} + +void cpu_gen_init(void) +{ +} + +int cpu_restore_state(TranslationBlock *tb, + CPUState *env, unsigned long searched_pc, + void *puc) + +{ + return 0; +} + +int cpu_x86_gen_code(CPUState *env, TranslationBlock *tb, int *gen_code_size_ptr) +{ + return 0; +} + +void optimize_flags_init(void) +{ +} diff --git a/target-i386/helper.c b/target-i386/helper.c index 957b3fc1f..fd32b2ee9 100644 --- a/target-i386/helper.c +++ b/target-i386/helper.c @@ -28,6 +28,8 @@ #include "qemu-common.h" #include "kvm.h" +#include "qemu-kvm.h" + //#define DEBUG_MMU /* feature flags taken from "Intel Processor Identification and the CPUID @@ -42,7 +44,7 @@ static const char *feature_name[] = { static const char *ext_feature_name[] = { "pni" /* Intel,AMD sse3 */, NULL, NULL, "monitor", "ds_cpl", "vmx", NULL /* Linux smx */, "est", "tm2", "ssse3", "cid", NULL, NULL, "cx16", "xtpr", NULL, - NULL, NULL, "dca", NULL, NULL, NULL, NULL, "popcnt", + NULL, NULL, "dca", NULL, NULL, "x2apic", NULL, "popcnt", NULL, NULL, NULL, NULL, NULL, NULL, NULL, "hypervisor", }; static const char *ext2_feature_name[] = { @@ -1544,6 +1546,11 @@ void cpu_inject_x86_mce(CPUState *cenv, int bank, uint64_t status, unsigned bank_num = mcg_cap & 0xff; uint64_t *banks = cenv->mce_banks; + if (kvm_enabled()) { + kvm_inject_x86_mce(cenv, bank, status, mcg_status, addr, misc, 0); + return; + } + if (bank >= bank_num || !(status & MCI_STATUS_VAL)) return; @@ -1607,7 +1614,7 @@ static void host_cpuid(uint32_t function, uint32_t count, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx) { -#if defined(CONFIG_KVM) +#if defined(CONFIG_KVM) || defined(USE_KVM) uint32_t vec[4]; #ifdef __x86_64__ @@ -1767,8 +1774,29 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, } if (kvm_enabled()) { - /* Nested SVM not yet supported in KVM */ - *ecx &= ~CPUID_EXT3_SVM; + uint32_t h_eax, h_edx; + + host_cpuid(index, 0, &h_eax, NULL, NULL, &h_edx); + + /* disable CPU features that the host does not support */ + + /* long mode */ + if ((h_edx & 0x20000000) == 0 /* || !lm_capable_kernel */) + *edx &= ~0x20000000; + /* syscall */ + if ((h_edx & 0x00000800) == 0) + *edx &= ~0x00000800; + /* nx */ + if ((h_edx & 0x00100000) == 0) + *edx &= ~0x00100000; + + /* disable CPU features that KVM cannot support */ + + /* svm */ + if (!kvm_nested) + *ecx &= ~CPUID_EXT3_SVM; + /* 3dnow */ + *edx &= ~0xc0000000; } else { /* AMD 3DNow! is not supported in QEMU */ *edx &= ~(CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT); @@ -1886,8 +1914,6 @@ CPUX86State *cpu_x86_init(const char *cpu_model) } mce_init(env); - qemu_init_vcpu(env); - return env; } diff --git a/target-i386/kvm.c b/target-i386/kvm.c index 701099921..24c990367 100644 --- a/target-i386/kvm.c +++ b/target-i386/kvm.c @@ -24,6 +24,7 @@ #include "cpu.h" #include "gdbstub.h" +#ifdef KVM_UPSTREAM //#define DEBUG_KVM #ifdef DEBUG_KVM @@ -477,6 +478,7 @@ static int kvm_put_msrs(CPUState *env) if (kvm_has_msr_star(env)) kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star); kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc); + kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave); #ifdef TARGET_X86_64 /* FIXME if lm capable */ kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar); @@ -610,6 +612,7 @@ static int kvm_get_msrs(CPUState *env) if (kvm_has_msr_star(env)) msrs[n++].index = MSR_STAR; msrs[n++].index = MSR_IA32_TSC; + msrs[n++].index = MSR_VM_HSAVE_PA; #ifdef TARGET_X86_64 /* FIXME lm_capable_kernel */ msrs[n++].index = MSR_CSTAR; @@ -653,6 +656,9 @@ static int kvm_get_msrs(CPUState *env) case MSR_IA32_TSC: env->tsc = msrs[i].data; break; + case MSR_VM_HSAVE_PA: + env->vm_hsave = msrs[i].data; + break; } } @@ -683,10 +689,6 @@ int kvm_arch_put_registers(CPUState *env) if (ret < 0) return ret; - ret = kvm_get_mp_state(env); - if (ret < 0) - return ret; - return 0; } @@ -746,6 +748,7 @@ int kvm_arch_pre_run(CPUState *env, struct kvm_run *run) return 0; } +#endif int kvm_arch_post_run(CPUState *env, struct kvm_run *run) { @@ -760,6 +763,7 @@ int kvm_arch_post_run(CPUState *env, struct kvm_run *run) return 0; } +#ifdef KVM_UPSTREAM static int kvm_handle_halt(CPUState *env) { if (!((env->interrupt_request & CPU_INTERRUPT_HARD) && @@ -957,3 +961,6 @@ void kvm_arch_update_guest_debug(CPUState *env, struct kvm_guest_debug *dbg) } } #endif /* KVM_CAP_SET_GUEST_DEBUG */ +#endif + +#include "qemu-kvm-x86.c" diff --git a/target-i386/libkvm.h b/target-i386/libkvm.h new file mode 100644 index 000000000..d85b6a1e0 --- /dev/null +++ b/target-i386/libkvm.h @@ -0,0 +1,28 @@ +/* + * This header is for functions & variables that will ONLY be + * used inside libkvm for x86. + * THESE ARE NOT EXPOSED TO THE USER AND ARE ONLY FOR USE + * WITHIN LIBKVM. + * + * derived from libkvm.c + * + * Copyright (C) 2006 Qumranet, Inc. + * + * Authors: + * Avi Kivity <avi@qumranet.com> + * Yaniv Kamay <yaniv@qumranet.com> + * + * This work is licensed under the GNU LGPL license, version 2. + */ + +#ifndef KVM_X86_H +#define KVM_X86_H + +#define PAGE_SIZE 4096ul +#define PAGE_MASK (~(PAGE_SIZE - 1)) + +int kvm_set_tss_addr(kvm_context_t kvm, unsigned long addr); + +#define smp_wmb() asm volatile("" ::: "memory") + +#endif diff --git a/target-i386/machine.c b/target-i386/machine.c index 869c681f4..2b88fea63 100644 --- a/target-i386/machine.c +++ b/target-i386/machine.c @@ -6,6 +6,7 @@ #include "exec-all.h" #include "kvm.h" +#include "qemu-kvm.h" static const VMStateDescription vmstate_segment = { .name = "segment", @@ -323,6 +324,7 @@ static void cpu_pre_save(void *opaque) int i, bit; cpu_synchronize_state(env); + kvm_save_mpstate(env); /* FPU */ env->fpus_vmstate = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11; @@ -384,6 +386,8 @@ static int cpu_post_load(void *opaque, int version_id) } tlb_flush(env, 1); + kvm_load_mpstate(env); + return 0; } @@ -475,6 +479,9 @@ static const VMStateDescription vmstate_cpu = { VMSTATE_UINT64_ARRAY_V(mce_banks, CPUState, MCE_BANKS_DEF *4, 10), /* rdtscp */ VMSTATE_UINT64_V(tsc_aux, CPUState, 11), + /* KVM pvclock msr */ + VMSTATE_UINT64_V(system_time_msr, CPUState, 12), + VMSTATE_UINT64_V(wall_clock_msr, CPUState, 12), VMSTATE_END_OF_LIST() } }; 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