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* gas: Add --gdwarf-cie-version command line flagAndrew Burgess2019-11-1813-2/+125
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a flag to control the version of CIE that is generated. By default gas produces CIE version 1, and this continues to be the default after this patch. However, a user can now provide --gdwarf-cie-version=NUMBER to switch to either version 3 or version 4 of CIE, version 2 was never released, and so causes an error as does any number less than 1 or greater than 4. Producing version 4 CIE requires two new fields to be added to the CIE, an address size field, and an segment selector field. For a flat address space the DWARF specification indicates that the segment selector should be 0, and the address size fields just contains the address size in bytes. For now we support 4 or 8 byte addresses, and the segment selector is always produced as 0. At some future time we might need to allow targets to override this. gas/ChangeLog: * as.c (parse_args): Parse --gdwarf-cie-version option. (flag_dwarf_cie_version): New variable. * as.h (flag_dwarf_cie_version): Declare. * dw2gencfi.c (output_cie): Switch from DW_CIE_VERSION to flag_dwarf_cie_version. * doc/as.texi (Overview): Document --gdwarf-cie-version. * NEWS: Likewise. * testsuite/gas/cfi/cfi.exp: Add new tests. * testsuite/gas/cfi/cie-version-0.d: New file. * testsuite/gas/cfi/cie-version-1.d: New file. * testsuite/gas/cfi/cie-version-2.d: New file. * testsuite/gas/cfi/cie-version-3.d: New file. * testsuite/gas/cfi/cie-version-4.d: New file. * testsuite/gas/cfi/cie-version.s: New file. include/ChangeLog: * dwarf2.h (DW_CIE_VERSION): Delete. Change-Id: I9de19461aeb8332b5a57bbfe802953d0725a7ae8
* x86: fold individual Jump* attributes into a single Jump oneJan Beulich2019-11-143-34/+41
| | | | ..., taking just 3 bits instead of 5. No two of them are used together.
* x86: make JumpAbsolute an insn attributeJan Beulich2019-11-143-21/+45
| | | | | ... instead of an operand one: There's only ever one operand here anyway.
* x86: make AnySize an insn attributeJan Beulich2019-11-142-1/+5
| | | | | | ... instead of an operand one. Which operand it applies to can be determined from other operand properties, but as it turns out the only place it is actually used at doesn't even need further qualification.
* x86/Intel: correct CMPSD test cases' regexp closing paren placementJan Beulich2019-11-143-39/+45
| | | | | | The CMPS test case derivation from their MOVS counterparts I did in d241b91073 ("x86/Intel: correct MOVSD and CMPSD handling") ended up with misplaced closing parentheses in som regexps. Correct this.
* x86/Intel: extend MOVSD/CMPSD testsuite coverageJan Beulich2019-11-1410-0/+386
| | | | This is still in the context of PR/gas 25167.
* RISC-V: Support the INSN_CLASS.*F.* classes for .insn directive.Jim Wilson2019-11-122-1/+5
| | | | | | | | | | | | | | | | We have to enable the f extension through -march or ELF attribute if we use the FPR in .insn directive. The behavior is same as the riscv_opcodes. 2019-11-12 Nelson Chu <nelson.chu@sifive.com> opcodes/ * riscv-opc.c (riscv_insn_types): Replace the INSN_CLASS_I with INSN_CLASS_F and the INSN_CLASS_C with INSN_CLASS_F_AND_C if we use the floating point register (FPR). gas/ * testsuite/gas/riscv/insn.d: Add the f extension to -march option. Change-Id: I4f59d04c82673ef84c56ecd2659ad8ce164dd626
* [gas][arm] Enable VLDM, VSTM, VPUSH, VPOP for MVEMihail Ionescu2019-11-124-44/+131
| | | | | | | | | | | | | | | | | | | | | | | | | This patch enables a few instructions for Armv8.1-M MVE. Currently VLDM, VSTM, VSTR, VLDR, VPUSH and VPOP are enabled only when the Armv8-M Floating-point Extension is enabled. According to the ARMv8.1-M ARM, section A.1.4.2[1], they can be enabled by having "Armv8-M Floating-point Extension and/or Armv8.1-M MVE". [1]https://developer.arm.com/docs/ddi0553/bh/armv81-m-architecture-reference-manual 2019-11-12 Mihail Ionescu <mihail.ionescu@arm.com> * config/tc-arm.c (do_vfp_nsyn_push): Move in order to enable it for both fpu_vfp_ext_v1xd and mve_ext and add call to the aliased vstm instruction for mve_ext. (do_vfp_nsyn_pop): Move in order to enable it for both fpu_vfp_ext_v1xd and mve_ext and add call to the aliased vldm instruction for mve_ext. (do_neon_ldm_stm): Add fpu_vfp_ext_v1 and mve_ext checks. (insns): Enable vldm, vldmia, vldmdb, vstm, vstmia, vstmdb, vpop, vpush, and fldd, fstd, flds, fsts for arm_ext_v6t2 instead of fpu_vfp_ext_v1xd. * testsuite/gas/arm/v8_1m-mve.s: New. * testsuite/gas/arm/v8_1m-mve.d: New.
* [binutils][arm] Update the decoding of MVE VMOV, VMVNMihail Ionescu2019-11-124-2/+94
| | | | | | | | | | | | | | | | | | | | | This patch updates the decoding of the VMOV and VMVN instructions which depend on cmode. Previously VMOV and VMVN with cmode 1101 were not allowed. The cmode changes also required updating of the MVE conflict checking. Now instructions with opcodes 0xef800d50 and 0xef800e70 correctly get decoded as VMOV and VMVN, respectively. 2019-11-12 Mihail Ionescu <mihail.ionescu@arm.com> * opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with cmode 1101. (is_mve_encoding_conflict): Update cmode conflict checks for MVE_VMVN_IMM. 2019-11-12 Mihail Ionescu <mihail.ionescu@arm.com> * gas/config/tc-arm.c (do_neon_mvn): Allow mve_ext cmode=0xd. * testsuite/gas/arm/mve-vmov-vmvn-vorr-vbic.s: New test. * testsuite/gas/arm/mve-vmov-vmvn-vorr-vbic.d: Likewise.
* [gas][arm] Make .fpu reset the FPU/Coprocessor feature bitsMihail Ionescu2019-11-125-2/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is fixes the '.fpu' behaviour. Currently, using '.fpu' resets the previously selected '.fpu' options (by overwriting them), but does not reset previous FPU options selected by other means (ie. when using '.arch_extension fp' in conjunction with '.fpu <x>', the FPU is not reset). Example: .arch armv8-a @ SET BASE .arch_extension fp @ ADD FP-ARMV8 .fpu vfpv2 @ ADD (already existing bits, does not reset) vfms.f32 s0, s1, s2 @ OK .arch armv8-a @ RESET .fpu fp-armv8 @ ADD FP-ARMV8 vfms.f32 s0, s1, s2 @ OK .fpu vfpv2 @ RESET to VFPV2 vfms.f32 s0, s1, s2 @ ERROR After the patch this becomes: .arch armv8-a @ SET BASE .arch_extension fp @ ADD FP-ARMV8 .fpu vfpv2 @ RESET TO VFPV2 vfms.f32 s0, s1, s2 @ ERROR .arch armv8-a @ RESET .fpu fp-armv8 @ ADD FP-ARMV8 vfms.f32 s0, s1, s2 @ OK .fpu vfpv2 @ RESET to VFPV2 vfms.f32 s0, s1, s2 @ ERROR gas/ChangeLog: 2019-11-11 Mihail Ionescu <mihail.ionescu@arm.com> * config/tc-arm.c (s_arm_fpu): Clear selected_cpu fpu bits. (fpu_any): Remove OBJ_ELF guards. * gas/testsuite/gas/arm/fpu-rst.s: New. * gas/testsuite/gas/arm/fpu-rst.d: New. * gas/testsuite/gas/arm/fpu-rst.l: New.
* x86: fold EsSeg into IsStringJan Beulich2019-11-122-34/+31
| | | | | | | | | | | | | | EsSeg (a per-operand bit) is used with IsString (a per-insn attribute) only. Extend the attribute to 2 bits, thus allowing to encode - not a string insn, - string insn with neither operand requiring use of %es:, - string insn with 1st operand requiring use of %es:, - string insn with 2nd operand requiring use of %es:, which covers all possible cases, allowing to drop EsSeg. The (transient) need to comment out the OTUnused #define did uncover an oversight in the earlier OTMax -> OTNum conversion, which is being taken care of here.
* x86: eliminate ImmExt abuseJan Beulich2019-11-1212-352/+343
| | | | | | | | Drop the remaining instances left in place by commit c3949f432f ("x86: limit ImmExt abuse), now that we have a way to specify specific GPRs. Take the opportunity and also introduce proper 16-bit forms of applicable SVME insns as well as 1-operand forms of CLZERO.
* x86: introduce operand type "instance"Jan Beulich2019-11-122-29/+55
| | | | | | | | | | | Special register "class" instances can't be combined with one another (neither in templates nor in register entries), and hence it is not a good use of resources (memory as well as execution time) to represent them as individual bits of a bit field. Furthermore the generalization becoming possible will allow improvements to the handling of insns accepting only individual registers as their operands.
* Arm64: SVE2's smaxp/sminp require operands 1 and 3 to be the same registerJan Beulich2019-11-113-0/+10
| | | | This is just like for their umaxp/uminp and fmaxp/fminp counterparts.
* i386: Only check suffix in instruction mnemonicH.J. Lu2019-11-086-44/+69
| | | | | | | | | | | | | | | | | | | | | | | | | | We should check suffix in instruction mnemonic when matching instruction. In Intel syntax, normally we check for memory operand size. But the same mnemonic with 2 different encodings can have the same memory operand size and i.suffix is set to LONG_DOUBLE_MNEM_SUFFIX from memory operand size in Intel syntax to distinguish them. When there is no suffix in mnemonic, we check LONG_DOUBLE_MNEM_SUFFIX in i.suffix for mnemonic suffix. gas/ PR gas/25167 * config/tc-i386.c (match_template): Don't check instruction suffix set from operand. * testsuite/gas/i386/code16.d: New file. * testsuite/gas/i386/code16.s: Likewise. * testsuite/gas/i386/i386.exp: Run code16. * testsuite/gas/i386/x86-64-branch-4.l: Updated. opcodes/ PR gas/25167 * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd. * i386-tbl.h: Regenerated.
* x86: convert RegMask and RegBND from bitfield to enumeratorJan Beulich2019-11-082-6/+13
| | | | This is to further shrink the operand type representation.
* x86: convert RegSIMD and RegMMX from bitfield to enumeratorJan Beulich2019-11-082-43/+53
| | | | This is to further shrink the operand type representation.
* x86: convert Control/Debug/Test from bitfield to enumeratorJan Beulich2019-11-082-14/+20
| | | | This is to further shrink the operand type representation.
* x86: convert SReg from bitfield to enumeratorJan Beulich2019-11-083-9/+18
| | | | This is to further shrink the operand type representation.
* x86: introduce operand type "class"Jan Beulich2019-11-082-41/+73
| | | | | | | Many operand types, in particular the various kinds of registers, can't be combined with one another (neither in templates nor in register entries), and hence it is not a good use of resources (memory as well as execution time) to represent them as individual bits of a bit field.
* [gas][aarch64] Add the v8.6 Data Gathering Hint mnemonic [10/X]Matthew Malcomson2019-11-073-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Hi, This patch is part of a series that adds support for Armv8.6-A to binutils. In this last patch, the new Data Gathering Hint mnemonic is introduced. Committed on behalf of Mihail Ionescu. gas/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> * testsuite/gas/aarch64/dgh.s: New test. * testsuite/gas/aarch64/dgh.d: New test. opcodes/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions. (aarch64_opcode_table): Add data gathering hint mnemonic. * opcodes/aarch64-dis-2.c: Account for new instruction. Is it ok for trunk? Regards, Mihail
* [Patch][binutils][arm] Armv8.6-A Matrix Multiply extension [9/10]Matthew Malcomson2019-11-076-5/+171
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Hi, This patch is part of a series that adds support for Armv8.6-A (Matrix Multiply and BFloat16 extensions) to binutils. This patch introduces the Matrix Multiply (Int8, F32, F64) extensions to the arm backend. The following Matrix Multiply instructions are added: vummla, vsmmla, vusmmla, vusdot, vsudot[1]. [1]https://developer.arm.com/docs/ddi0597/latest/simd-and-floating-point-instructions-alphabetic-order Committed on behalf of Mihail Ionescu. gas/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> * config/tc-arm.c (arm_ext_i8mm): New feature set. (do_vusdot): New. (do_vsudot): New. (do_vsmmla): New. (do_vummla): New. (insns): Add vsmmla, vummla, vusmmla, vusdot, vsudot mnemonics. (armv86a_ext_table): Add i8mm extension. (arm_extensions): Move bf16 extension to context sensitive table. (armv82a_ext_table, armv84a_ext_table, armv85a_ext_table): Move bf16 extension to context sensitive table. (armv86a_ext_table): Add i8mm extension. * doc/c-arm.texi: Document i8mm extension. * testsuite/gas/arm/i8mm.s: New test. * testsuite/gas/arm/i8mm.d: New test. * testsuite/gas/arm/bfloat17-cmdline-bad-3.d: Update test. include/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> * opcode/arm.h (ARM_EXT2_I8MM): New feature macro. opcodes/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions. Regression tested on arm-none-eabi. Is this ok for trunk? Regards, Mihail
* [binutils][aarch64] Matrix Multiply extension enablement [8/X]Matthew Malcomson2019-11-0711-0/+330
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Hi, This patch is part of a series that adds support for Armv8.6-A (Matrix Multiply and BFloat16 extensions) to binutils. This patch introduces the Matrix Multiply (Int8, F32, F64) extensions to the aarch64 backend. The following instructions are added: {s/u}mmla, usmmla, {us/su}dot, fmmla, ld1rob, ld1roh, d1row, ld1rod, uzip{1/2}, trn{1/2}. Committed on behalf of Mihail Ionescu. gas/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> * config/tc-aarch64.c: Add new arch fetures to suppport the mm extension. (parse_operands): Add new operand. * testsuite/gas/aarch64/i8mm.s: New test. * testsuite/gas/aarch64/i8mm.d: New test. * testsuite/gas/aarch64/f32mm.s: New test. * testsuite/gas/aarch64/f32mm.d: New test. * testsuite/gas/aarch64/f64mm.s: New test. * testsuite/gas/aarch64/f64mm.d: New test. * testsuite/gas/aarch64/sve-movprfx-mm.s: New test. * testsuite/gas/aarch64/sve-movprfx-mm.d: New test. include/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_I8MM): New. (AARCH64_FEATURE_F32MM): New. (AARCH64_FEATURE_F64MM): New. (AARCH64_OPND_SVE_ADDR_RI_S4x32): New. (enum aarch64_insn_class): Add new instruction class "aarch64_misc" for instructions that do not require special handling. opcodes/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve, aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm, aarch64_feature_f64mm): New feature sets. (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN, F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply instructions. (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set macros. (QL_MMLA64, OP_SVE_SBB): New qualifiers. (OP_SVE_QQQ): New qualifier. (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC, F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support the movprfx constraint. (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32. (aarch64_opcode_table): Define new instructions smmla, ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod uzip{1/2}, trn{1/2}. * aarch64-opc.c (operand_general_constraint_met_p): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32. (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32. * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode): Account for new instructions. * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new S4x32 operand. * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand. Regression tested on arm-none-eabi. Is it ok for trunk? Regards, Mihail
* [Patch][binutils][aarch64] .bfloat16 directive for AArch64 [7/10]Matthew Malcomson2019-11-075-0/+98
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Hi, This patch is part of a series that adds support for Armv8.6-A (Matrix Multiply and BFloat16 extensions) to binutils. This patch implements the '.bfloat' directive for the AArch64 backend. The syntax for the directive is: .bfloat16 <0-n numbers> e.g. .bfloat16 12.0 .bfloat16 0.123, 1.0, NaN, 5 This is implemented by utilizing the ieee_atof_detail function in order to encode the slightly different bfloat16 format. Added testcases to verify the correct encoding for various bfloat16 values (NaN, Infinity (+ & -), normals, subnormals etc...). Cross compiled and tested on aarch64-none-elf and aarch64-none-linux-gnu with no issues. Committed on behalf of Mihail Ionescu. gas/ChangeLog: 2019-10-29 Mihail Ionescu <mihail.ionescu@arm.com> 2019-10-29 Barnaby Wilks <barnaby.wilks@arm.com> * config/tc-aarch64.c (md_atof): Add encoding for the bfloat16 format. * testsuite/gas/aarch64/bfloat16-directive-le.d: New test. * testsuite/gas/aarch64/bfloat16-directive-be.d: New test. * testsuite/gas/aarch64/bfloat16-directive.s: New test. Is it ok for trunk? Regards, Mihail
* [Patch][binutils][arm] .bfloat16 directive for Arm [6/X]Matthew Malcomson2019-11-075-0/+96
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Hi, This patch is part of a series that adds support for Armv8.6-A (Matrix Multiply and BFloat16 extensions) to binutils. This patch implements the '.bfloat16' directive for the Arm backend. The syntax for the directive is: .bfloat16 <0-n numbers> e.g. .bfloat16 12.0 .bfloat16 0.123, 1.0, NaN, 5 This is implemented by utilizing the ieee_atof_detail function (included in the previous patch) in order to encode the slightly different bfloat16 format. Added testcases to verify the correct encoding for various bfloat16 values (NaN, Infinity (+ & -), normals, subnormals etc...). Cross compiled and tested on arm-none-eabi and arm-none-linux-gnueabihf with no issues. Committed on behalf of Mihail Ionescu. gas/ChangeLog: 2019-10-21 Mihail Ionescu <mihail.ionescu@arm.com> 2019-10-21 Barnaby Wilks <barnaby.wilks@arm.com> * config/tc-arm.c (md_atof): Add encoding for bfloat16 * testsuite/gas/arm/bfloat16-directive-le.d: New test. * testsuite/gas/arm/bfloat16-directive-be.d: New test. * testsuite/gas/arm/bfloat16-directive.s: New test. Is it ok for trunk? Regards, Mihail
* [Patch][binutils] Generic support for parsing numbers in bfloat16 format [5/X]Matthew Malcomson2019-11-073-29/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Hi, This patch is part of a series that adds support for Armv8.6-A (Matrix Multiply and BFloat16 extensions). This patch contains some general refactoring of the atof_ieee function, exposing a function that allows a higher level of control over the format of IEEE-like floating point numbers. This has been done in order to be able to add a directive for assembling floating point literals in the bfloat16 format in the following patches. Committed on behalf of Mihail Ionescu. Tested on arm-none-eabi, arm-none-linux-gnueabihf, aarch64-none-elf and aarch64-none-linux-gnuwith no issues. gas/ChangeLog: 2019-10-21 Mihail Ionescu <mihail.ionescu@arm.com> 2019-10-21 Barnaby Wilks <barnaby.wilks@arm.com> * as.h (atof_ieee_detail): Add prototype for atof_ieee_detail function. (atof_ieee): Move some code into the atof_ieee_detail function. (atof_ieee_detail): Add function that provides a higher level of control over generating IEEE-like numbers. Is it ok for trunk? Regards, Mihail
* [binutils][arm] BFloat16 enablement [4/X]Matthew Malcomson2019-11-0718-24/+807
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Hi, This patch is part of a series that adds support for Armv8.6-A (Matrix Multiply and BFloat16 extensions) to binutils. This patch introduces BFloat16 instructions to the arm backend. The following BFloat16 instructions are added: vdot, vfma{l/t}, vmmla, vfmal{t/b}, vcvt, vcvt{t/b}. gas/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-arm.c (arm_archs): Add armv8.6-a option. (cpu_arch_ver): Add TAG_CPU_ARCH_V8 tag for Armv8.6-a. * doc/c-arm.texi (-march): New armv8.6-a arch. * config/tc-arm.c (arm_ext_bf16): New feature set. (enum neon_el_type): Add NT_bfloat value. (B_MNEM_vfmat, B_MNEM_vfmab): New bfloat16 encoder helpers. (BAD_BF16): New message. (parse_neon_type): Add bf16 type specifier. (enum neon_type_mask): Add N_BF16 type. (type_chk_of_el_type): Account for NT_bfloat. (el_type_of_type_chk): Account for N_BF16. (neon_three_args): Split out from neon_three_same. (neon_three_same): Part split out into neon_three_args. (CVT_FLAVOUR_VAR): Add bf16_f32 cvt flavour. (do_neon_cvt_1): Account for vcvt.bf16.f32. (do_bfloat_vmla): New. (do_mve_vfma): New function to deal with the mnemonic clash between the BF16 vfmat and the MVE vfma in a VPT block with a 't'rue condition. (do_neon_cvttb_1): Account for vcvt{t,b}.bf16.f32. (do_vdot): New (do_vmmla): New (insns): Add vdot and vmmla mnemonics. (arm_extensions): Add "bf16" extension. * doc/c-arm.texi: Document "bf16" extension. * testsuite/gas/arm/attr-march-armv8_6-a.d: New test. * testsuite/gas/arm/bfloat16-bad.d: New test. * testsuite/gas/arm/bfloat16-bad.l: New test. * testsuite/gas/arm/bfloat16-bad.s: New test. * testsuite/gas/arm/bfloat16-cmdline-bad-2.d: New test. * testsuite/gas/arm/bfloat16-cmdline-bad-3.d: New test. * testsuite/gas/arm/bfloat16-cmdline-bad.d: New test. * testsuite/gas/arm/bfloat16-neon.s: New test. * testsuite/gas/arm/bfloat16-non-neon.s: New test. * testsuite/gas/arm/bfloat16-thumb-bad.d: New test. * testsuite/gas/arm/bfloat16-thumb-bad.l: New test. * testsuite/gas/arm/bfloat16-thumb.d: New test. * testsuite/gas/arm/bfloat16-vfp.d: New test. * testsuite/gas/arm/bfloat16.d: New test. * testsuite/gas/arm/bfloat16.s: New test. include/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/arm.h (ARM_EXT2_V8_6A, ARM_AEXT2_V8_6A, ARM_ARCH_V8_6A): New. * opcode/arm.h (ARM_EXT2_BF16): New feature macro. (ARM_AEXT2_V8_6A): Include above macro in definition. opcodes/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com> * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with Armv8.6-A. (coprocessor_opcodes): Add bfloat16 vcvt{t,b}. (neon_opcodes): Add bfloat SIMD instructions. (print_insn_coprocessor): Add new control character %b to print condition code without checking cp_num. (print_insn_neon): Account for BFloat16 instructions that have no special top-byte handling. Regression tested on arm-none-eabi. Is it ok for trunk? Regards, Mihail
* [binutils][aarch64] Bfloat16 enablement [2/X]Matthew Malcomson2019-11-0710-0/+372
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Hi, This patch is part of a series that adds support for Armv8.6-A (Matrix Multiply and BFloat16 extensions) to binutils. This patch introduces the following BFloat16 instructions to the aarch64 backend: bfdot, bfmmla, bfcvt, bfcvtnt, bfmlal[t/b], bfcvtn2. Committed on behalf of Mihail Ionescu. gas/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-aarch64.c (vectype_to_qualifier): Special case the S_2H operand qualifier. * doc/c-aarch64.texi: Document bf16 and bf16mmla4 extensions. * testsuite/gas/aarch64/bfloat16.d: New test. * testsuite/gas/aarch64/bfloat16.s: New test. * testsuite/gas/aarch64/illegal-bfloat16.d: New test. * testsuite/gas/aarch64/illegal-bfloat16.l: New test. * testsuite/gas/aarch64/illegal-bfloat16.s: New test. * testsuite/gas/aarch64/sve-bfloat-movprfx.s: New test. * testsuite/gas/aarch64/sve-bfloat-movprfx.d: New test. include/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_BFLOAT16): New feature macros. (AARCH64_ARCH_V8_6): Include BFloat16 feature macros. (enum aarch64_opnd_qualifier): Introduce new operand qualifier AARCH64_OPND_QLF_S_2H. (enum aarch64_insn_class): Introduce new class "bfloat16". (BFLOAT16_SVE_INSNC): New feature set for bfloat16 instructions to support the movprfx constraint. opcodes/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H in reglane special case. * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode): Account for new instructions. * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H in reglane special case. * aarch64-opc.c (struct operand_qualifier_data): Add data for new AARCH64_OPND_QLF_S_2H qualifier. * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2, QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers. (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve, aarch64_feature_bfloat16_bfmmla4): New feature sets. (BFLOAT_SVE, BFLOAT): New feature set macros. (BFLOAT_SVE_INSN, BFLOAT_BFMMLA4_INSN, BFLOAT_INSN): New macros to define BFloat16 instructions. (aarch64_opcode_table): Define new instructions bfdot, bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t] bfcvtn2, bfcvt. Regression tested on aarch64-elf. Is it ok for trunk? Regards, Mihail
* [gas][aarch64] Armv8.6-a option [1/X]Matthew Malcomson2019-11-073-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Hi, This patch is part of a series that adds support for Armv8.6-A to binutils. This first patch adds the Armv8.6-A flag to binutils. No instructions are behind it at the moment. Commited on behalf of Mihail Ionescu. gas/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-aarch64.c (armv8.6-a): New arch. * doc/c-aarch64.texi (armv8.6-a): Document new arch. include/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_V8_6): New. (AARCH64_ARCH_V8_6): New. opcodes/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-tbl.h (ARMV8_6): New macro. Is it ok for trunk? Regards, Mihail
* x86: support further AMD Zen2 instructionsJan Beulich2019-11-0710-55/+45
| | | | | Both RDPRU and MCOMMIT have been publicly documented meanwhile: https://www.amd.com/system/files/TechDocs/24594.pdf.
* x86: adjust register names printed for MONITOR/MWAITJan Beulich2019-11-0712-201/+80
| | | | | | | | | | As the comments (here: almost, in the opcode table: fully) correctly state - all register operands except MONITOR's address one are fixed at 32 bit size. Don't print 64-bit registers there. Also adjust x86-64-suffix.d's name such that it wouldn't be identical to x86-64-rep-suffix.d's, but instead resemble that of its sibling x86-64-suffix-intel.d.
* x86: re-arrange process_operands()Jan Beulich2019-11-042-57/+54
| | | | | | | | | Alter the sequence of conditions evaluated, without affecting the overall result. This is going to help subsequent changes (and as a nice side effect also slightly reduces overall indentation depth). While doing this take the liberty of simplifying the calculation of the operand index of the register operand in ShortForm handling.
* i386; Add .code16gcc fldenv testsH.J. Lu2019-10-313-2/+20
| | | | | * testsuite/gas/i386/general.s: Add .code16gcc fldenv tests. * testsuite/gas/i386/general.l: Updated.
* Add support for context sensitive '.arch_extension' to the ARM assembler.Mihail Ionescu2019-10-316-0/+68
| | | | | | | | | | | | | | | | | If the extension is not found in the context sensitive table, the legacy tables are still checked as a fallback. This is particularly useful for Armv8.1-M as it enables the use of '.arch_extension' with the 'mve' and 'mve.fp' extensions which are not part of the legacy table. * config/tc-arm.c (selected_ctx_ext_table) New static variable. (arm_parse_arch): Set context sensitive extension table based on the chosen base architecture. (s_arm_arch_extension): Change to lookup extensions in the new context sensitive tables. * gas/testsuite/gas/arm/mve-ext.s: New. * gas/testsuite/gas/arm/mve-ext.d: New. * gas/testsuite/gas/arm/mvefp-ext.s: New. * gas/testsuite/gas/arm/mvefp-ext.d: New.
* Modify the ARNM assembler to accept the omission of the immediate argument ↵Delia Burduv2019-10-306-44/+86
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | for the writeback form of the LDRAA and LDRAB mnemonics This is a shorthand for the immediate argument being 0, as described here: https://developer.arm.com/docs/ddi0596/latest/base-instructions-alphabetic-order/ldraa-ldrab-load-register-with-pointer-authentication This is because the instructions still have a use with an immediate argument of 0, unlike loads without the PAC functionality. Currently, the mnemonics are LDRAA Xt, [Xn, #<simm10>]! LDRAB Xt, [Xn, #<simm10>]! After this patch they become LDRAA Xt, [Xn {, #<simm10>}]! LDRAB Xt, [Xn {, #<simm10>}]! gas * config/tc-aarch64.c (parse_address_main): Accept the omission of the immediate argument for ldraa and ldrab as a shorthand for the immediate being 0. * testsuite/gas/aarch64/ldraa-ldrab-no-offset.d: New test. * testsuite/gas/aarch64/ldraa-ldrab-no-offset.s: New test. * testsuite/gas/aarch64/illegal-ldraa.s: Modified to accept the writeback form with no offset. * testsuite/gas/aarch64/illegal-ldraa.s: Removed missing offset error. opcodes * aarch64-opc.c (print_immediate_offset_address): Don't print the immediate for the writeback form of ldraa/ldrab if it is 0. * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10. * aarch64-opc-2.c: Regenerated.
* x86: add tests to cover defaulting of operand sizes for ambiguous insnsJan Beulich2019-10-308-0/+392
| | | | | | | | | | | | | | | | Prior to changing the logic in the assembler install tests to make sure the present defaulting of operand sizes won't get broken. There are a few anomalies pointed out by this: - arithmetic insns (add, sub, etc) allow defaulting when their immediate fits in (signed) 8 bits, but they fail to assemble with larger values, - mov, other than arithmetic insns, doesn't allow any defaulting, - movsx/movzx default to byte sources (in AT&T mode), and their special casing needs to be adjusted first - bt and friends allow defaulting, while shl and friends don't, - ambiguous AVX and AVX512 insns don't allow defaulting. This should ultimately all become consistent (perhaps with the exception some of the SIMD insns); respective tests will be added to the test cases here as the issues get addressed.
* x86: drop stray WJan Beulich2019-10-302-5/+11
| | | | | | | | | | | The flag is used to indicate opcodes which can be switched between byte and word/dword/qword forms (in a "canonical" way). Obviously it's quite odd then to see it on insns not allowing for byte operands in the first place. As a result the opcode bytes need to be adjusted accordingly, which includes comparisons done in optimize_encoding(). To make re-introduction of such issues less likely have i386-gen diagnose it (in a generally non-fatal way for now).
* Re: Optimise away eh_frame advance_loc 0Alan Modra2019-10-292-1/+12
| | | | | | | | | | If we happen to get the fixed and variable parts of the advance_loc in different frags, bad things happen when subtracting one from a fr_fix of zero. PR 25125 * dw2gencfi.c (output_cfi_insn): Don't allow DW_CFA_advance_loc4 to be placed in a different frag to the rs_cfa.
* Add some missing casts to suppress implicit cast warningsJohn David Anglin2019-10-262-5/+12
| | | | | | PR gas/25121 * config/tc-hppa.c (tc_gen_reloc): Cast some enums to int. (md_assemble): Likewise.
* Optimise away eh_frame advance_loc 0Alan Modra2019-10-263-4/+28
| | | | | | | | | | | | | | | | | | | These can be generated when multiple cfi directives are emitted for an instruction and the insn frag is closed off between directives, as happens when listings are enabled. No doubt the advance_loc of zero could be avoided by backtracking over frags in dw2gencfi.c before calling cfi_add_advance_loc, but that seems like more work than cleaning up afterwards as this patch does. Noticed when looking at the testcase in PR25125. PR 25125 * dw2gencfi.c (output_cfi_insn): Don't output DW_CFA_advance_loc+0. * ehopt.c (eh_frame_estimate_size_before_relax): Return -1 for an advance_loc of zero. (eh_frame_relax_frag): Translate fr_subtype of 7 to size -1. (eh_frame_convert_frag): Handle fr_subtype of 7. Abort on unexpected fr_subtype.
* PR25125, relaxation chooses wrong branch sizeAlan Modra2019-10-252-4/+13
| | | | | | | | | | | | | | | | | The patch I made for PR12049 didn't test for a "negative" branch properly. "if (target < address)" ought to have been "if (target < address + fragP->fr_fix)". Rather than making that change, this patch adds fragP->fr_fix into address earlier. The patch also avoids running into a bad interaction with the m68k md_prepare_relax_scan by returning zero growth immediately, since the adjusted target expression would result in a zero "aim". PR gas/25125 PR gas/12049 * write.c (relax_frag): Correct calculation of delta for positive branches where "stretch" would make the branch negative. Return zero immediately in that case. Correct TC_PCREL_ADJUST comment.
* qsort: tc-xtensa.c tidyAlan Modra2019-10-162-22/+33
| | | | | | | | | | Not much to see here, just reduce the number of calls to S_GET_VALUE and symbol_symbolS in the comparison functions. * config/tc-xtensa.c (xg_order_trampoline_chain_entry): Don't call S_GET_VALUE multiple times for a symbol. Rearrange code so it is obvious what is the primary sort key. (xg_order_trampoline_chain): Similarly.
* remove more xmalloc in bfdAlan Modra2019-10-152-6/+12
| | | | | | | | | | | | | | | | | | Also fixes m68hc1x printf arguments which would have bombed when compiling on a 32-bit host with --enable-64-bit-bfd. bfd/ PR 24955 * elf32-arm.c (set_cmse_veneer_addr_from_implib): Use bfd_malloc rather than xmalloc. * elf32-m68hc1x.c (reloc_warning): New function. (elf32_m68hc11_relocate_section): Use it here. Cast bfd_vma values corresponding to %lx in format strings. * elf32-nds32.c (nds32_insertion_sort): Use a stack temporary. gas/ * config/tc-nds32.c (nds32_set_section_relocs): Use relocs and n parameters rather than equivalent sec->orelocation and sec->reloc_count. Don't sort for n <= 1. Tidy.
* Fix the disassembly of the LDS and STS instructions of the AVR architecture.Nick Clifton2019-10-093-0/+19
| | | | | | | | | PR 25041 opcodes * avr-dis.c (avr_operand): Fix construction of address for lds/sts instructions. gas * testsuite/gas/avr/pr25041.s: New test. * testsuite/gas/avr/pr25041.d: New test driver.
* S/390: Add support for z15 as CPU name.Andreas Krebbel2019-10-083-4/+5
| | | | | | | | | | | | | | | | | | | | | So far z15 was identified as arch13. After the machine has been announced we can now add the real name. gas/ChangeLog: 2019-10-08 Andreas Krebbel <krebbel@linux.ibm.com> * config/tc-s390.c (s390_parse_cpu): Add z15 as alternate CPU name. * doc/as.texi: Add z15 to CPU string list. * doc/c-s390.texi: Likewise. opcodes/ChangeLog: 2019-10-08 Andreas Krebbel <krebbel@linux.ibm.com> * s390-mkopc.c (main): Enable z15 as CPU string in the opcode table.
* Add support for new functionality in the msp430 backend of GCC.Jozef Lawrynowicz2019-10-0717-4/+252
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This functionality will generate a new GNU object attribute for the "data region" has been added. This object attribute is used mark whether the compiler has generated code assuming that data could be in the upper or lower memory regions. Code which assumes data is always in the lower memory region is incompatible with code which uses the full memory range for data. The patch also adds a new assembler directive ".mspabi_attribute" to handle the existing MSPABI object attributes. GCC will now emit both .gnu_attribute and .mspabi_attribute directives to indicate what options the source file was compiled with. The assembler will now check the values set in these directives against the options that the it has been invoked with. If there is a discrepancy, the assembler will exit with an error. bfd * elf32-msp430.c (elf32_msp430_merge_mspabi_attributes): Rename to.. (elf32_msp430_merge_msp430_attributes): Add support for merging the GNU object attribute for data region. binutils* readelf.c (display_msp430_gnu_attribute): New. (process_arch_specific): Use msp430 specific handler for GNU attributes. gas * config/tc-msp430.c (md_parse_option): Set lower_data_region_only to FALSE if the data region is set to "upper", "either" or "none". (msp430_object_attribute): New. (md_pseudo_table): Handle .mspabi_attribute and .gnu_attribute. (msp430_md_end): Replace hard-coded attribute values with enums. Handle data region object attribute. * doc/as.texi: Document MSP430 Data Region object attribute. * doc/c-msp430.texi: Document the .mspabi_attribute directive. * testsuite/gas/msp430/attr-430-small-bad.d: New test. * testsuite/gas/msp430/attr-430-small-bad.l: New test. * testsuite/gas/msp430/attr-430-small-good.d: New test. * testsuite/gas/msp430/attr-430-small.s: New test. * testsuite/gas/msp430/attr-430x-large-any-bad.d: New test. * testsuite/gas/msp430/attr-430x-large-any-bad.l: New test. * testsuite/gas/msp430/attr-430x-large-any-good.d: New test. * testsuite/gas/msp430/attr-430x-large-any.s: New test. * testsuite/gas/msp430/attr-430x-large-lower-bad.d: New test. * testsuite/gas/msp430/attr-430x-large-lower-bad.l: New test. * testsuite/gas/msp430/attr-430x-large-lower-good.d: New test. * testsuite/gas/msp430/attr-430x-large-lower.s: New test. * testsuite/gas/msp430/msp430.exp: Run new tests. include * elf/msp430.h: Add enums for MSPABI and GNU object attribute tag names and values. ld * testsuite/ld-msp430-elf/attr-gnu-main.s: New test. * testsuite/ld-msp430-elf/attr-gnu-obj.s: New test. * testsuite/ld-msp430-elf/attr-gnu-region-lower-upper.d: New test. * testsuite/ld-msp430-elf/attr-gnu-region-lower.d: New test. * testsuite/ld-msp430-elf/attr-gnu-region-upper.d: New test. * testsuite/ld-msp430-elf/msp430-elf.exp: Run new tests.
* add missing ChangeLog entry for d241b91073Jan Beulich2019-10-071-0/+13
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* x86/Intel: correct MOVSD and CMPSD handlingJan Beulich2019-10-079-12/+233
| | | | | | | First and foremost the EsSeg attribute was misplaced for CMPSD. Then both it and MOVSD were lacking Dword on both of their operands. Finally string insns with multiple operands and requiring use of ES: had the wrong operand number reported in the diagnostic.
* Arm: Fix out of range conditional branch (PR/24991)Tamar Christina2019-09-245-7/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The fix for PR12848 introduced an off by one error in the mask, this corrected the negative overflows but not the positive overflows. As a result the conditional branch instructions accepted a too wide positive immediate which resulted in it corrupting the instruction during encoding. The relocation I believe has been incorrectly named, to be consistent with the other relocations it should have been named BRANCH21 which is why the masks for it are confusing. I've replaced the masks with a function out_of_range_p which should make it harder to make such mistakes. The mask for BL/BLX on Armv6t+ is also wrong, the extended range is 25-bits and so the mask should be checking for 24-bits for positive overflow. gas/ChangeLog: PR gas/24991 * config/tc-arm.c (out_of_range_p): New. (md_apply_fix): Use it in BFD_RELOC_THUMB_PCREL_BRANCH9, BFD_RELOC_THUMB_PCREL_BRANCH12, BFD_RELOC_THUMB_PCREL_BRANCH20, BFD_RELOC_THUMB_PCREL_BRANCH23, BFD_RELOC_THUMB_PCREL_BRANCH25 * testsuite/gas/arm/pr24991.d: New test. * testsuite/gas/arm/pr24991.l: New test. * testsuite/gas/arm/pr24991.s: New test.
* [ARM]: Modify assembler to accept floating and signless datatypes for MVE ↵Srinath Parvathaneni2019-09-245-6/+81
| | | | | | | | | | | | | | | | | | instruction VLDR. This patch modifies assembler to accept the equivalent sized floating and signless datatypes for VLDR instruction but as alias for the unsigned version. gas/ChangeLog: 2019-09-23 Srinath Parvathaneni <srinath.parvathaneni@arm.com> * config/tc-arm.c (do_mve_vstr_vldr_RQ): Modify function to allow float * and signless datatypes for few cases of VLDR instruction. * testsuite/gas/arm/mve-vldr-bad-3.l: Modify. * testsuite/gas/arm/mve-vldr-bad-3.s: Likewise. * testsuite/gas/arm/mve-vstrldr-1.d: Likewise. * testsuite/gas/arm/mve-vstrldr-1.s: Likewise.